1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __SOC_ROCKCHIP_RK3328_GRF_H__ 8 #define __SOC_ROCKCHIP_RK3328_GRF_H__ 9 10 struct rk3328_grf_regs { 11 u32 gpio0a_iomux; 12 u32 gpio0b_iomux; 13 u32 gpio0c_iomux; 14 u32 gpio0d_iomux; 15 u32 gpio1a_iomux; 16 u32 gpio1b_iomux; 17 u32 gpio1c_iomux; 18 u32 gpio1d_iomux; 19 u32 gpio2a_iomux; 20 u32 gpio2bl_iomux; 21 u32 gpio2bh_iomux; 22 u32 gpio2cl_iomux; 23 u32 gpio2ch_iomux; 24 u32 gpio2d_iomux; 25 u32 gpio3al_iomux; 26 u32 gpio3ah_iomux; 27 u32 gpio3bl_iomux; 28 u32 gpio3bh_iomux; 29 u32 gpio3c_iomux; 30 u32 gpio3d_iomux; 31 u32 com_iomux; 32 u32 reserved1[(0x100 - 0x54) / 4]; 33 34 u32 gpio0a_p; 35 u32 gpio0b_p; 36 u32 gpio0c_p; 37 u32 gpio0d_p; 38 u32 gpio1a_p; 39 u32 gpio1b_p; 40 u32 gpio1c_p; 41 u32 gpio1d_p; 42 u32 gpio2a_p; 43 u32 gpio2b_p; 44 u32 gpio2c_p; 45 u32 gpio2d_p; 46 u32 gpio3a_p; 47 u32 gpio3b_p; 48 u32 gpio3c_p; 49 u32 gpio3d_p; 50 u32 reserved2[(0x200 - 0x140) / 4]; 51 u32 gpio0a_e; 52 u32 gpio0b_e; 53 u32 gpio0c_e; 54 u32 gpio0d_e; 55 u32 gpio1a_e; 56 u32 gpio1b_e; 57 u32 gpio1c_e; 58 u32 gpio1d_e; 59 u32 gpio2a_e; 60 u32 gpio2b_e; 61 u32 gpio2c_e; 62 u32 gpio2d_e; 63 u32 gpio3a_e; 64 u32 gpio3b_e; 65 u32 gpio3c_e; 66 u32 gpio3d_e; 67 u32 reserved3[(0x300 - 0x240) / 4]; 68 u32 gpio0l_sr; 69 u32 gpio0h_sr; 70 u32 gpio1l_sr; 71 u32 gpio1h_sr; 72 u32 gpio2l_sr; 73 u32 gpio2h_sr; 74 u32 gpio3l_sr; 75 u32 gpio3h_sr; 76 u32 reserved4[(0x380 - 0x320) / 4]; 77 u32 gpio0l_smt; 78 u32 gpio0h_smt; 79 u32 gpio1l_smt; 80 u32 gpio1h_smt; 81 u32 gpio2l_smt; 82 u32 gpio2h_smt; 83 u32 gpio3l_smt; 84 u32 gpio3h_smt; 85 u32 reserved5[(0x400 - 0x3a0) / 4]; 86 u32 soc_con[11]; 87 u32 reserved6[(0x480 - 0x42c) / 4]; 88 u32 soc_status[5]; 89 u32 reserved7[(0x4c0 - 0x494) / 4]; 90 u32 otg3_con[2]; 91 u32 reserved8[(0x500 - 0x4c8) / 4]; 92 u32 cpu_con[2]; 93 u32 reserved9[(0x520 - 0x508) / 4]; 94 u32 cpu_status[2]; 95 u32 reserved10[(0x5c8 - 0x528) / 4]; 96 u32 os_reg[8]; 97 u32 reserved11[(0x680 - 0x5e8) / 4]; 98 u32 sig_detect_con; 99 u32 reserved12[3]; 100 u32 sig_detect_status; 101 u32 reserved13[3]; 102 u32 sig_detect_status_clr; 103 u32 reserved14[3]; 104 105 u32 sdmmc_det_counter; 106 u32 reserved15[(0x700 - 0x6b4) / 4]; 107 u32 host0_con[3]; 108 u32 reserved16[(0x880 - 0x70c) / 4]; 109 u32 otg_con0; 110 u32 reserved17[3]; 111 u32 host0_status; 112 u32 reserved18[(0x900 - 0x894) / 4]; 113 u32 mac_con[3]; 114 u32 reserved19[(0xb00 - 0x90c) / 4]; 115 u32 macphy_con[4]; 116 u32 macphy_status; 117 }; 118 check_member(rk3328_grf_regs, macphy_status, 0xb10); 119 120 struct rk3328_sgrf_regs { 121 u32 soc_con[6]; 122 u32 reserved0[(0x100 - 0x18) / 4]; 123 u32 dmac_con[6]; 124 u32 reserved1[(0x180 - 0x118) / 4]; 125 u32 fast_boot_addr; 126 u32 reserved2[(0x200 - 0x184) / 4]; 127 u32 chip_fuse_con; 128 u32 reserved3[(0x280 - 0x204) / 4]; 129 u32 hdcp_key_reg[8]; 130 u32 hdcp_key_access_mask; 131 }; 132 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); 133 134 enum { 135 /* GPIO0A_IOMUX */ 136 GPIO0A5_SEL_SHIFT = 10, 137 GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, 138 GPIO0A5_I2C3_SCL = 2, 139 140 GPIO0A6_SEL_SHIFT = 12, 141 GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, 142 GPIO0A6_I2C3_SDA = 2, 143 144 GPIO0A7_SEL_SHIFT = 14, 145 GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, 146 GPIO0A7_EMMC_DATA0 = 2, 147 148 /* GPIO0D_IOMUX*/ 149 GPIO0D6_SEL_SHIFT = 12, 150 GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, 151 GPIO0D6_GPIO = 0, 152 GPIO0D6_SDMMC0_PWRENM1 = 3, 153 154 /* GPIO1A_IOMUX */ 155 GPIO1A0_SEL_SHIFT = 0, 156 GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, 157 GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, 158 159 /* GPIO2A_IOMUX */ 160 GPIO2A0_SEL_SHIFT = 0, 161 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, 162 GPIO2A0_UART2_TX_M1 = 1, 163 164 GPIO2A1_SEL_SHIFT = 2, 165 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, 166 GPIO2A1_UART2_RX_M1 = 1, 167 168 GPIO2A2_SEL_SHIFT = 4, 169 GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, 170 GPIO2A2_PWM_IR = 1, 171 172 GPIO2A4_SEL_SHIFT = 8, 173 GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, 174 GPIO2A4_PWM_0 = 1, 175 GPIO2A4_I2C1_SDA, 176 177 GPIO2A5_SEL_SHIFT = 10, 178 GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, 179 GPIO2A5_PWM_1 = 1, 180 GPIO2A5_I2C1_SCL, 181 182 GPIO2A6_SEL_SHIFT = 12, 183 GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, 184 GPIO2A6_PWM_2 = 1, 185 186 GPIO2A7_SEL_SHIFT = 14, 187 GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, 188 GPIO2A7_GPIO = 0, 189 GPIO2A7_SDMMC0_PWRENM0, 190 191 /* GPIO2BL_IOMUX */ 192 GPIO2BL0_SEL_SHIFT = 0, 193 GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, 194 GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, 195 196 GPIO2BL3_SEL_SHIFT = 6, 197 GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, 198 GPIO2BL3_SPI_CSN0_M0 = 1, 199 200 GPIO2BL4_SEL_SHIFT = 8, 201 GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, 202 GPIO2BL4_SPI_CSN1_M0 = 1, 203 204 GPIO2BL5_SEL_SHIFT = 10, 205 GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, 206 GPIO2BL5_I2C2_SDA = 1, 207 208 GPIO2BL6_SEL_SHIFT = 12, 209 GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, 210 GPIO2BL6_I2C2_SCL = 1, 211 212 /* GPIO2D_IOMUX */ 213 GPIO2D0_SEL_SHIFT = 0, 214 GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, 215 GPIO2D0_I2C0_SCL = 1, 216 217 GPIO2D1_SEL_SHIFT = 2, 218 GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, 219 GPIO2D1_I2C0_SDA = 1, 220 221 GPIO2D4_SEL_SHIFT = 8, 222 GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, 223 GPIO2D4_EMMC_DATA1234 = 0xaa, 224 225 /* GPIO3C_IOMUX */ 226 GPIO3C0_SEL_SHIFT = 0, 227 GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, 228 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, 229 230 /* COM_IOMUX */ 231 IOMUX_SEL_UART2_SHIFT = 0, 232 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, 233 IOMUX_SEL_UART2_M0 = 0, 234 IOMUX_SEL_UART2_M1, 235 236 IOMUX_SEL_SPI_SHIFT = 4, 237 IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, 238 IOMUX_SEL_SPI_M0 = 0, 239 IOMUX_SEL_SPI_M1, 240 IOMUX_SEL_SPI_M2, 241 242 IOMUX_SEL_SDMMC_SHIFT = 7, 243 IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, 244 IOMUX_SEL_SDMMC_M0 = 0, 245 IOMUX_SEL_SDMMC_M1, 246 }; 247 248 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ 249