1 /* 2 * Copyright (c) 2015 Google, Inc 3 * Copyright 2014 Rockchip Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_EDP_H 9 #define _ASM_ARCH_EDP_H 10 11 struct rk3288_edp { 12 u8 res0[0x10]; 13 u32 dp_tx_version; 14 u8 res1[0x4]; 15 u32 func_en_1; 16 u32 func_en_2; 17 u32 video_ctl_1; 18 u32 video_ctl_2; 19 u32 video_ctl_3; 20 u32 video_ctl_4; 21 u8 res2[0xc]; 22 u32 video_ctl_8; 23 u8 res3[0x4]; 24 u32 video_ctl_10; 25 u32 total_line_l; 26 u32 total_line_h; 27 u32 active_line_l; 28 u32 active_line_h; 29 u32 v_f_porch; 30 u32 vsync; 31 u32 v_b_porch; 32 u32 total_pixel_l; 33 u32 total_pixel_h; 34 u32 active_pixel_l; 35 u32 active_pixel_h; 36 u32 h_f_porch_l; 37 u32 h_f_porch_h; 38 u32 hsync_l; 39 u32 hysnc_h; 40 u32 h_b_porch_l; 41 u32 h_b_porch_h; 42 u32 vid_status; 43 u32 total_line_sta_l; 44 u32 total_line_sta_h; 45 u32 active_line_sta_l; 46 u32 active_line_sta_h; 47 u32 v_f_porch_sta; 48 u32 vsync_sta; 49 u32 v_b_porch_sta; 50 u32 total_pixel_sta_l; 51 u32 total_pixel_sta_h; 52 u32 active_pixel_sta_l; 53 u32 active_pixel_sta_h; 54 u32 h_f_porch_sta_l; 55 u32 h_f_porch_sta_h; 56 u32 hsync_sta_l; 57 u32 hsync_sta_h; 58 u32 h_b_porch_sta_l; 59 u32 h_b_porch__sta_h; 60 u8 res4[0x28]; 61 u32 pll_reg_1; 62 u8 res5[4]; 63 u32 ssc_reg; 64 u8 res6[0xc]; 65 u32 tx_common; 66 u32 tx_common2; 67 u8 res7[0x4]; 68 u32 dp_aux; 69 u32 dp_bias; 70 u32 dp_test; 71 u32 dp_pd; 72 u32 dp_reserv1; 73 u32 dp_reserv2; 74 u8 res8[0x224]; 75 u32 lane_map; 76 u8 res9[0x14]; 77 u32 analog_ctl_2; 78 u8 res10[0x48]; 79 u32 int_state; 80 u32 common_int_sta_1; 81 u32 common_int_sta_2; 82 u32 common_int_sta_3; 83 u32 common_int_sta_4; 84 u32 spdif_biphase_int_sta; 85 u8 res11[0x4]; 86 u32 dp_int_sta; 87 u32 common_int_mask_1; 88 u32 common_int_mask_2; 89 u32 common_int_mask_3; 90 u32 common_int_mask_4; 91 u8 res12[0x08]; 92 u32 int_sta_mask; 93 u32 int_ctl; 94 u8 res13[0x200]; 95 u32 sys_ctl_1; 96 u32 sys_ctl_2; 97 u32 sys_ctl_3; 98 u32 sys_ctl_4; 99 u32 dp_vid_ctl; 100 u8 res14[0x4]; 101 u32 dp_aud_ctl; 102 u8 res15[0x24]; 103 u32 pkt_send_ctl; 104 u8 res16[0x4]; 105 u32 dp_hdcp_ctl; 106 u8 res17[0x34]; 107 u32 link_bw_set; 108 u32 lane_count_set; 109 u32 dp_training_ptn_set; 110 u32 ln_link_trn_ctl[4]; 111 u8 res18[0x4]; 112 u32 dp_hw_link_training; 113 u8 res19[0x1c]; 114 u32 dp_debug_ctl; 115 u32 hpd_deglitch_l; 116 u32 hpd_deglitch_h; 117 u8 res20[0x14]; 118 u32 dp_link_debug_ctl; 119 u8 res21[0x1c]; 120 u32 m_vid_0; 121 u32 m_vid_1; 122 u32 m_vid_2; 123 u32 n_vid_0; 124 u32 n_vid_1; 125 u32 n_vid_2; 126 u32 m_vid_mon; 127 u8 res22[0x14]; 128 u32 dp_video_fifo_thrd; 129 u8 res23[0x8]; 130 u32 dp_audio_margin; 131 u8 res24[0x20]; 132 u32 dp_m_cal_ctl; 133 u32 m_vid_gen_filter_th; 134 u8 res25[0x10]; 135 u32 m_aud_gen_filter_th; 136 u8 res26[0x4]; 137 u32 aux_ch_sta; 138 u32 aux_err_num; 139 u32 aux_ch_defer_dtl; 140 u32 aux_rx_comm; 141 u32 buf_data_ctl; 142 u32 aux_ch_ctl_1; 143 u32 aux_addr_7_0; 144 u32 aux_addr_15_8; 145 u32 aux_addr_19_16; 146 u32 aux_ch_ctl_2; 147 u8 res27[0x18]; 148 u32 buf_data[16]; 149 u32 soc_general_ctl; 150 u8 res29[0x1e0]; 151 u32 pll_reg_2; 152 u32 pll_reg_3; 153 u32 pll_reg_4; 154 u8 res30[0x10]; 155 u32 pll_reg_5; 156 }; 157 check_member(rk3288_edp, pll_reg_5, 0xa00); 158 159 /* func_en_1 */ 160 #define VID_CAP_FUNC_EN_N (0x1 << 6) 161 #define VID_FIFO_FUNC_EN_N (0x1 << 5) 162 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 163 #define AUD_FUNC_EN_N (0x1 << 3) 164 #define HDCP_FUNC_EN_N (0x1 << 2) 165 #define SW_FUNC_EN_N (0x1 << 0) 166 167 /* func_en_2 */ 168 #define SSC_FUNC_EN_N (0x1 << 7) 169 #define AUX_FUNC_EN_N (0x1 << 2) 170 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 171 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 172 173 /* video_ctl_1 */ 174 #define VIDEO_EN (0x1 << 7) 175 #define VIDEO_MUTE (0x1 << 6) 176 177 /* video_ctl_2 */ 178 #define IN_D_RANGE_MASK (0x1 << 7) 179 #define IN_D_RANGE_SHIFT (7) 180 #define IN_D_RANGE_CEA (0x1 << 7) 181 #define IN_D_RANGE_VESA (0x0 << 7) 182 #define IN_BPC_MASK (0x7 << 4) 183 #define IN_BPC_SHIFT (4) 184 #define IN_BPC_12_BITS (0x3 << 4) 185 #define IN_BPC_10_BITS (0x2 << 4) 186 #define IN_BPC_8_BITS (0x1 << 4) 187 #define IN_BPC_6_BITS (0x0 << 4) 188 #define IN_COLOR_F_MASK (0x3 << 0) 189 #define IN_COLOR_F_SHIFT (0) 190 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 191 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 192 #define IN_COLOR_F_RGB (0x0 << 0) 193 194 /* video_ctl_3 */ 195 #define IN_YC_COEFFI_MASK (0x1 << 7) 196 #define IN_YC_COEFFI_SHIFT (7) 197 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 198 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 199 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 200 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 201 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 202 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 203 204 /* video_ctl_4 */ 205 #define BIST_EN (0x1 << 3) 206 #define BIST_WH_64 (0x1 << 2) 207 #define BIST_WH_32 (0x0 << 2) 208 #define BIST_TYPE_COLR_BAR (0x0 << 0) 209 #define BIST_TYPE_GRAY_BAR (0x1 << 0) 210 #define BIST_TYPE_MOBILE_BAR (0x2 << 0) 211 212 /* video_ctl_8 */ 213 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 214 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 215 216 /* video_ctl_10 */ 217 #define F_SEL (0x1 << 4) 218 #define INTERACE_SCAN_CFG (0x1 << 2) 219 #define INTERACD_SCAN_CFG_OFFSET 2 220 #define VSYNC_POLARITY_CFG (0x1 << 1) 221 #define VSYNC_POLARITY_CFG_OFFSET 1 222 #define HSYNC_POLARITY_CFG (0x1 << 0) 223 #define HSYNC_POLARITY_CFG_OFFSET 0 224 225 /* dp_pd */ 226 #define PD_INC_BG (0x1 << 7) 227 #define PD_EXP_BG (0x1 << 6) 228 #define PD_AUX (0x1 << 5) 229 #define PD_PLL (0x1 << 4) 230 #define PD_CH3 (0x1 << 3) 231 #define PD_CH2 (0x1 << 2) 232 #define PD_CH1 (0x1 << 1) 233 #define PD_CH0 (0x1 << 0) 234 235 /* pll_reg_1 */ 236 #define REF_CLK_24M (0x1 << 1) 237 #define REF_CLK_27M (0x0 << 1) 238 239 /* line_map */ 240 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 241 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 242 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 243 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 244 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 245 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 246 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 247 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 248 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 249 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 250 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 251 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 252 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 253 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 254 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 255 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 256 257 /* analog_ctl_2 */ 258 #define SEL_24M (0x1 << 3) 259 260 /* common_int_sta_1 */ 261 #define VSYNC_DET (0x1 << 7) 262 #define PLL_LOCK_CHG (0x1 << 6) 263 #define SPDIF_ERR (0x1 << 5) 264 #define SPDIF_UNSTBL (0x1 << 4) 265 #define VID_FORMAT_CHG (0x1 << 3) 266 #define AUD_CLK_CHG (0x1 << 2) 267 #define VID_CLK_CHG (0x1 << 1) 268 #define SW_INT (0x1 << 0) 269 270 /* common_int_sta_2 */ 271 #define ENC_EN_CHG (0x1 << 6) 272 #define HW_BKSV_RDY (0x1 << 3) 273 #define HW_SHA_DONE (0x1 << 2) 274 #define HW_AUTH_STATE_CHG (0x1 << 1) 275 #define HW_AUTH_DONE (0x1 << 0) 276 277 /* common_int_sta_3 */ 278 #define AFIFO_UNDER (0x1 << 7) 279 #define AFIFO_OVER (0x1 << 6) 280 #define R0_CHK_FLAG (0x1 << 5) 281 282 /* common_int_sta_4 */ 283 #define PSR_ACTIVE (0x1 << 7) 284 #define PSR_INACTIVE (0x1 << 6) 285 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 286 #define HOTPLUG_CHG (0x1 << 2) 287 #define HPD_LOST (0x1 << 1) 288 #define PLUG (0x1 << 0) 289 290 /* dp_int_sta */ 291 #define INT_HPD (0x1 << 6) 292 #define HW_LT_DONE (0x1 << 5) 293 #define SINK_LOST (0x1 << 3) 294 #define LINK_LOST (0x1 << 2) 295 #define RPLY_RECEIV (0x1 << 1) 296 #define AUX_ERR (0x1 << 0) 297 298 /* int_ctl */ 299 #define SOFT_INT_CTRL (0x1 << 2) 300 #define INT_POL (0x1 << 0) 301 302 /* sys_ctl_1 */ 303 #define DET_STA (0x1 << 2) 304 #define FORCE_DET (0x1 << 1) 305 #define DET_CTRL (0x1 << 0) 306 307 /* sys_ctl_2 */ 308 #define CHA_CRI(x) (((x) & 0xf) << 4) 309 #define CHA_STA (0x1 << 2) 310 #define FORCE_CHA (0x1 << 1) 311 #define CHA_CTRL (0x1 << 0) 312 313 /* sys_ctl_3 */ 314 #define HPD_STATUS (0x1 << 6) 315 #define F_HPD (0x1 << 5) 316 #define HPD_CTRL (0x1 << 4) 317 #define HDCP_RDY (0x1 << 3) 318 #define STRM_VALID (0x1 << 2) 319 #define F_VALID (0x1 << 1) 320 #define VALID_CTRL (0x1 << 0) 321 322 /* sys_ctl_4 */ 323 #define FIX_M_AUD (0x1 << 4) 324 #define ENHANCED (0x1 << 3) 325 #define FIX_M_VID (0x1 << 2) 326 #define M_VID_UPDATE_CTRL (0x3 << 0) 327 328 /* pll_reg_2 */ 329 #define LDO_OUTPUT_V_SEL_145 (2 << 6) 330 #define KVCO_DEFALUT (1 << 4) 331 #define CHG_PUMP_CUR_SEL_5US (1 << 2) 332 #define V2L_CUR_SEL_1MA (1 << 0) 333 334 /* pll_reg_3 */ 335 #define LOCK_DET_CNT_SEL_256 (2 << 5) 336 #define LOOP_FILTER_RESET (0 << 4) 337 #define PALL_SSC_RESET (0 << 3) 338 #define LOCK_DET_BYPASS (0 << 2) 339 #define PLL_LOCK_DET_MODE (0 << 1) 340 #define PLL_LOCK_DET_FORCE (0 << 0) 341 342 /* pll_reg_5 */ 343 #define REGULATOR_V_SEL_950MV (2 << 4) 344 #define STANDBY_CUR_SEL (0 << 3) 345 #define CHG_PUMP_INOUT_CTRL_1200MV (1 << 1) 346 #define CHG_PUMP_INPUT_CTRL_OP (0 << 0) 347 348 /* ssc_reg */ 349 #define SSC_OFFSET (0 << 6) 350 #define SSC_MODE (1 << 4) 351 #define SSC_DEPTH (9 << 0) 352 353 /* tx_common */ 354 #define TX_SWING_PRE_EMP_MODE (1 << 7) 355 #define PRE_DRIVER_PW_CTRL1 (0 << 5) 356 #define LP_MODE_CLK_REGULATOR (0 << 4) 357 #define RESISTOR_MSB_CTRL (0 << 3) 358 #define RESISTOR_CTRL (7 << 0) 359 360 /* dp_aux */ 361 #define DP_AUX_COMMON_MODE (0 << 4) 362 #define DP_AUX_EN (0 << 3) 363 #define AUX_TERM_50OHM (3 << 0) 364 365 /* dp_bias */ 366 #define DP_BG_OUT_SEL (4 << 4) 367 #define DP_DB_CUR_CTRL (0 << 3) 368 #define DP_BG_SEL (1 << 2) 369 #define DP_RESISTOR_TUNE_BG (2 << 0) 370 371 /* dp_reserv2 */ 372 #define CH1_CH3_SWING_EMP_CTRL (5 << 4) 373 #define CH0_CH2_SWING_EMP_CTRL (5 << 0) 374 375 /* dp_training_ptn_set */ 376 #define SCRAMBLING_DISABLE (0x1 << 5) 377 #define SCRAMBLING_ENABLE (0x0 << 5) 378 #define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2) 379 #define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2) 380 #define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2) 381 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 382 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 383 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 384 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 385 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 386 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 387 #define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0) 388 389 /* dp_hw_link_training_ctl */ 390 #define HW_LT_ERR_CODE_MASK 0x70 391 #define HW_LT_ERR_CODE_SHIFT 4 392 #define HW_LT_EN (0x1 << 0) 393 394 /* dp_debug_ctl */ 395 #define PLL_LOCK (0x1 << 4) 396 #define F_PLL_LOCK (0x1 << 3) 397 #define PLL_LOCK_CTRL (0x1 << 2) 398 #define POLL_EN (0x1 << 1) 399 #define PN_INV (0x1 << 0) 400 401 /* aux_ch_sta */ 402 #define AUX_BUSY (0x1 << 4) 403 #define AUX_STATUS_MASK (0xf << 0) 404 405 /* aux_ch_defer_ctl */ 406 #define DEFER_CTRL_EN (0x1 << 7) 407 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 408 409 /* aux_rx_comm */ 410 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 411 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 412 413 /* buffer_data_ctl */ 414 #define BUF_CLR (0x1 << 7) 415 #define BUF_HAVE_DATA (0x1 << 4) 416 #define BUF_DATA_COUNT(x) (((x) & 0xf) << 0) 417 418 /* aux_ch_ctl_1 */ 419 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 420 #define AUX_TX_COMM_MASK (0xf << 0) 421 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 422 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 423 #define AUX_TX_COMM_MOT (0x1 << 2) 424 #define AUX_TX_COMM_WRITE (0x0 << 0) 425 #define AUX_TX_COMM_READ (0x1 << 0) 426 427 /* aux_ch_ctl_2 */ 428 #define PD_AUX_IDLE (0x1 << 3) 429 #define ADDR_ONLY (0x1 << 1) 430 #define AUX_EN (0x1 << 0) 431 432 /* tx_sw_reset */ 433 #define RST_DP_TX (0x1 << 0) 434 435 /* analog_ctl_1 */ 436 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 437 438 /* analog_ctl_3 */ 439 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 440 #define VCO_BIT_600_MICRO (0x5 << 0) 441 442 /* pll_filter_ctl_1 */ 443 #define PD_RING_OSC (0x1 << 6) 444 #define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4) 445 #define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4) 446 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 447 #define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4) 448 #define TX_CUR1_2X (0x1 << 2) 449 #define TX_CUR_16_MA (0x3 << 0) 450 451 /* Definition for DPCD Register */ 452 #define DPCD_DPCD_REV (0x0000) 453 #define DPCD_MAX_LINK_RATE (0x0001) 454 #define DPCD_MAX_LANE_COUNT (0x0002) 455 #define DP_MAX_LANE_COUNT_MASK 0x1f 456 #define DP_TPS3_SUPPORTED (1 << 6) 457 #define DP_ENHANCED_FRAME_CAP (1 << 7) 458 459 #define DPCD_LINK_BW_SET (0x0100) 460 #define DPCD_LANE_COUNT_SET (0x0101) 461 462 #define DPCD_TRAINING_PATTERN_SET (0x0102) 463 #define DP_TRAINING_PATTERN_DISABLE 0 464 #define DP_TRAINING_PATTERN_1 1 465 #define DP_TRAINING_PATTERN_2 2 466 #define DP_TRAINING_PATTERN_3 3 467 #define DP_TRAINING_PATTERN_MASK 0x3 468 469 #define DPCD_TRAINING_LANE0_SET (0x0103) 470 #define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 471 #define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 472 #define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 473 #define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 474 #define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 475 #define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 476 #define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 477 478 #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 479 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 480 #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 481 #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 482 #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 483 484 #define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 485 #define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 486 487 #define DPCD_LANE0_1_STATUS (0x0202) 488 #define DPCD_LANE2_3_STATUS (0x0203) 489 #define DP_LANE_CR_DONE (1 << 0) 490 #define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 491 #define DP_LANE_SYMBOL_LOCKED (1 << 2) 492 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |\ 493 DP_LANE_CHANNEL_EQ_DONE |\ 494 DP_LANE_SYMBOL_LOCKED) 495 496 #define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204) 497 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 498 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 499 #define DP_LINK_STATUS_UPDATED (1 << 7) 500 501 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) 502 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) 503 #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 504 #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 505 #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 506 #define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 507 #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 508 #define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 509 #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 510 #define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 511 512 #define DPCD_TEST_REQUEST (0x0218) 513 #define DPCD_TEST_RESPONSE (0x0260) 514 #define DPCD_TEST_EDID_CHECKSUM (0x0261) 515 #define DPCD_LINK_POWER_STATE (0x0600) 516 #define DP_SET_POWER_D0 0x1 517 #define DP_SET_POWER_D3 0x2 518 #define DP_SET_POWER_MASK 0x3 519 520 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 521 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 522 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 523 524 #define STREAM_ON_TIMEOUT 100 525 #define PLL_LOCK_TIMEOUT 10 526 #define DP_INIT_TRIES 10 527 528 #define EDID_ADDR 0x50 529 #define EDID_LENGTH 0x80 530 #define EDID_HEADER 0x00 531 #define EDID_EXTENSION_FLAG 0x7e 532 533 534 enum dpcd_request { 535 DPCD_READ, 536 DPCD_WRITE, 537 }; 538 539 enum dp_irq_type { 540 DP_IRQ_TYPE_HP_CABLE_IN, 541 DP_IRQ_TYPE_HP_CABLE_OUT, 542 DP_IRQ_TYPE_HP_CHANGE, 543 DP_IRQ_TYPE_UNKNOWN, 544 }; 545 546 enum color_coefficient { 547 COLOR_YCBCR601, 548 COLOR_YCBCR709 549 }; 550 551 enum dynamic_range { 552 VESA, 553 CEA 554 }; 555 556 enum clock_recovery_m_value_type { 557 CALCULATED_M, 558 REGISTER_M 559 }; 560 561 enum video_timing_recognition_type { 562 VIDEO_TIMING_FROM_CAPTURE, 563 VIDEO_TIMING_FROM_REGISTER 564 }; 565 566 enum pattern_set { 567 PRBS7, 568 D10_2, 569 TRAINING_PTN1, 570 TRAINING_PTN2, 571 DP_NONE 572 }; 573 574 enum color_space { 575 CS_RGB, 576 CS_YCBCR422, 577 CS_YCBCR444 578 }; 579 580 enum color_depth { 581 COLOR_6, 582 COLOR_8, 583 COLOR_10, 584 COLOR_12 585 }; 586 587 enum link_rate_type { 588 LINK_RATE_1_62GBPS = 0x06, 589 LINK_RATE_2_70GBPS = 0x0a 590 }; 591 592 enum link_lane_count_type { 593 LANE_CNT1 = 1, 594 LANE_CNT2 = 2, 595 LANE_CNT4 = 4 596 }; 597 598 enum link_training_state { 599 LT_START, 600 LT_CLK_RECOVERY, 601 LT_EQ_TRAINING, 602 FINISHED, 603 FAILED 604 }; 605 606 enum voltage_swing_level { 607 VOLTAGE_LEVEL_0, 608 VOLTAGE_LEVEL_1, 609 VOLTAGE_LEVEL_2, 610 VOLTAGE_LEVEL_3, 611 }; 612 613 enum pre_emphasis_level { 614 PRE_EMPHASIS_LEVEL_0, 615 PRE_EMPHASIS_LEVEL_1, 616 PRE_EMPHASIS_LEVEL_2, 617 PRE_EMPHASIS_LEVEL_3, 618 }; 619 620 enum analog_power_block { 621 AUX_BLOCK, 622 CH0_BLOCK, 623 CH1_BLOCK, 624 CH2_BLOCK, 625 CH3_BLOCK, 626 ANALOG_TOTAL, 627 POWER_ALL 628 }; 629 630 struct link_train { 631 unsigned char revision; 632 u8 link_rate; 633 u8 lane_count; 634 }; 635 636 #endif 637