1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 #ifndef _ASM_ARCH_CRU_RV1108_H 7 #define _ASM_ARCH_CRU_RV1108_H 8 9 #include <common.h> 10 11 #define OSC_HZ (24 * 1000 * 1000) 12 13 #define APLL_HZ (600 * 1000000) 14 #define GPLL_HZ (1188 * 1000000) 15 #define ACLK_PERI_HZ (148500000) 16 #define HCLK_PERI_HZ (148500000) 17 #define PCLK_PERI_HZ (74250000) 18 #define ACLK_BUS_HZ (148500000) 19 20 struct rv1108_clk_priv { 21 struct rv1108_cru *cru; 22 ulong rate; 23 }; 24 25 struct rv1108_cru { 26 struct rv1108_pll { 27 unsigned int con0; 28 unsigned int con1; 29 unsigned int con2; 30 unsigned int con3; 31 unsigned int con4; 32 unsigned int con5; 33 unsigned int reserved[2]; 34 } pll[3]; 35 unsigned int clksel_con[46]; 36 unsigned int reserved1[2]; 37 unsigned int clkgate_con[20]; 38 unsigned int reserved2[4]; 39 unsigned int softrst_con[13]; 40 unsigned int reserved3[3]; 41 unsigned int glb_srst_fst_val; 42 unsigned int glb_srst_snd_val; 43 unsigned int glb_cnt_th; 44 unsigned int misc_con; 45 unsigned int glb_rst_con; 46 unsigned int glb_rst_st; 47 unsigned int sdmmc_con[2]; 48 unsigned int sdio_con[2]; 49 unsigned int emmc_con[2]; 50 }; 51 check_member(rv1108_cru, emmc_con[1], 0x01ec); 52 53 struct pll_div { 54 u32 refdiv; 55 u32 fbdiv; 56 u32 postdiv1; 57 u32 postdiv2; 58 u32 frac; 59 }; 60 61 enum { 62 /* PLL CON0 */ 63 FBDIV_MASK = 0xfff, 64 FBDIV_SHIFT = 0, 65 66 /* PLL CON1 */ 67 POSTDIV2_SHIFT = 12, 68 POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, 69 POSTDIV1_SHIFT = 8, 70 POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, 71 REFDIV_MASK = 0x3f, 72 REFDIV_SHIFT = 0, 73 74 /* PLL CON2 */ 75 LOCK_STA_SHIFT = 31, 76 LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, 77 FRACDIV_MASK = 0xffffff, 78 FRACDIV_SHIFT = 0, 79 80 /* PLL CON3 */ 81 WORK_MODE_SHIFT = 8, 82 WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, 83 WORK_MODE_SLOW = 0, 84 WORK_MODE_NORMAL = 1, 85 DSMPD_SHIFT = 3, 86 DSMPD_MASK = 1 << DSMPD_SHIFT, 87 INTEGER_MODE = 1, 88 GLOBAL_POWER_DOWN_SHIFT = 0, 89 GLOBAL_POWER_DOWN_MASK = 1 << GLOBAL_POWER_DOWN_SHIFT, 90 GLOBAL_POWER_DOWN = 1, 91 GLOBAL_POWER_UP = 0, 92 93 /* CLKSEL0_CON */ 94 CORE_PLL_SEL_SHIFT = 8, 95 CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, 96 CORE_PLL_SEL_APLL = 0, 97 CORE_PLL_SEL_GPLL = 1, 98 CORE_PLL_SEL_DPLL = 2, 99 CORE_CLK_DIV_SHIFT = 0, 100 CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, 101 102 /* CLKSEL_CON1 */ 103 PCLK_DBG_DIV_CON_SHIFT = 4, 104 PCLK_DBG_DIV_CON_MASK = 0xf << PCLK_DBG_DIV_CON_SHIFT, 105 ACLK_CORE_DIV_CON_SHIFT = 0, 106 ACLK_CORE_DIV_CON_MASK = 7 << ACLK_CORE_DIV_CON_SHIFT, 107 108 /* CLKSEL_CON2 */ 109 ACLK_BUS_PLL_SEL_SHIFT = 8, 110 ACLK_BUS_PLL_SEL_MASK = 3 << ACLK_BUS_PLL_SEL_SHIFT, 111 ACLK_BUS_PLL_SEL_GPLL = 0, 112 ACLK_BUS_PLL_SEL_APLL = 1, 113 ACLK_BUS_PLL_SEL_DPLL = 2, 114 ACLK_BUS_DIV_CON_SHIFT = 0, 115 ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 116 ACLK_BUS_DIV_CON_WIDTH = 5, 117 118 /* CLKSEL_CON3 */ 119 PCLK_BUS_DIV_CON_SHIFT = 8, 120 PCLK_BUS_DIV_CON_MASK = 0x1f << PCLK_BUS_DIV_CON_SHIFT, 121 HCLK_BUS_DIV_CON_SHIFT = 0, 122 HCLK_BUS_DIV_CON_MASK = 0x1f, 123 124 /* CLKSEL_CON4 */ 125 CLK_DDR_PLL_SEL_SHIFT = 8, 126 CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT, 127 CLK_DDR_DIV_CON_SHIFT = 0, 128 CLK_DDR_DIV_CON_MASK = 0x3 << CLK_DDR_DIV_CON_SHIFT, 129 130 /* CLKSEL_CON19 */ 131 CLK_I2C1_PLL_SEL_SHIFT = 15, 132 CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 133 CLK_I2C1_PLL_SEL_DPLL = 0, 134 CLK_I2C1_PLL_SEL_GPLL = 1, 135 CLK_I2C1_DIV_CON_SHIFT = 8, 136 CLK_I2C1_DIV_CON_MASK = 0x7f << CLK_I2C1_DIV_CON_SHIFT, 137 CLK_I2C0_PLL_SEL_SHIFT = 7, 138 CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 139 CLK_I2C0_DIV_CON_SHIFT = 0, 140 CLK_I2C0_DIV_CON_MASK = 0x7f, 141 I2C_DIV_CON_WIDTH = 7, 142 143 /* CLKSEL_CON20 */ 144 CLK_I2C3_PLL_SEL_SHIFT = 15, 145 CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 146 CLK_I2C3_PLL_SEL_DPLL = 0, 147 CLK_I2C3_PLL_SEL_GPLL = 1, 148 CLK_I2C3_DIV_CON_SHIFT = 8, 149 CLK_I2C3_DIV_CON_MASK = 0x7f << CLK_I2C3_DIV_CON_SHIFT, 150 CLK_I2C2_PLL_SEL_SHIFT = 7, 151 CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 152 CLK_I2C2_DIV_CON_SHIFT = 0, 153 CLK_I2C2_DIV_CON_MASK = 0x7f, 154 155 /* CLKSEL_CON22 */ 156 CLK_SARADC_DIV_CON_SHIFT= 0, 157 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 158 CLK_SARADC_DIV_CON_WIDTH= 10, 159 160 /* CLKSEL_CON23 */ 161 ACLK_PERI_PLL_SEL_SHIFT = 15, 162 ACLK_PERI_PLL_SEL_MASK = 1 << ACLK_PERI_PLL_SEL_SHIFT, 163 ACLK_PERI_PLL_SEL_GPLL = 0, 164 ACLK_PERI_PLL_SEL_DPLL = 1, 165 PCLK_PERI_DIV_CON_SHIFT = 10, 166 PCLK_PERI_DIV_CON_MASK = 0x1f << PCLK_PERI_DIV_CON_SHIFT, 167 HCLK_PERI_DIV_CON_SHIFT = 5, 168 HCLK_PERI_DIV_CON_MASK = 0x1f << HCLK_PERI_DIV_CON_SHIFT, 169 ACLK_PERI_DIV_CON_SHIFT = 0, 170 ACLK_PERI_DIV_CON_MASK = 0x1f, 171 PERI_DIV_CON_WIDTH = 5, 172 173 /* CLKSEL24_CON */ 174 MAC_PLL_SEL_SHIFT = 12, 175 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 176 MAC_PLL_SEL_APLL = 0, 177 MAC_PLL_SEL_GPLL = 1, 178 RMII_EXTCLK_SEL_SHIFT = 8, 179 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 180 MAC_CLK_DIV_MASK = 0x1f, 181 MAC_CLK_DIV_SHIFT = 0, 182 183 /* CLKSEL25_CON */ 184 EMMC_PLL_SEL_SHIFT = 12, 185 EMMC_PLL_SEL_MASK = 3 << EMMC_PLL_SEL_SHIFT, 186 EMMC_PLL_SEL_DPLL = 0, 187 EMMC_PLL_SEL_GPLL, 188 EMMC_PLL_SEL_OSC, 189 190 /* CLKSEL26_CON */ 191 EMMC_CLK_DIV_SHIFT = 8, 192 EMMC_CLK_DIV_MASK = 0xff << EMMC_CLK_DIV_SHIFT, 193 194 /* CLKSEL27_CON */ 195 SFC_PLL_SEL_SHIFT = 7, 196 SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 197 SFC_PLL_SEL_DPLL = 0, 198 SFC_PLL_SEL_GPLL = 1, 199 SFC_CLK_DIV_SHIFT = 0, 200 SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, 201 202 /* CLKSEL28_CON */ 203 ACLK_VIO1_PLL_SEL_SHIFT = 14, 204 ACLK_VIO1_PLL_SEL_MASK = 3 << ACLK_VIO1_PLL_SEL_SHIFT, 205 VIO_PLL_SEL_DPLL = 0, 206 VIO_PLL_SEL_GPLL = 1, 207 ACLK_VIO1_CLK_DIV_SHIFT = 8, 208 ACLK_VIO1_CLK_DIV_MASK = 0x1f << ACLK_VIO1_CLK_DIV_SHIFT, 209 CLK_VIO_DIV_CON_WIDTH = 5, 210 ACLK_VIO0_PLL_SEL_SHIFT = 6, 211 ACLK_VIO0_PLL_SEL_MASK = 3 << ACLK_VIO0_PLL_SEL_SHIFT, 212 ACLK_VIO0_CLK_DIV_SHIFT = 0, 213 ACLK_VIO0_CLK_DIV_MASK = 0x1f << ACLK_VIO0_CLK_DIV_SHIFT, 214 215 /* CLKSEL29_CON */ 216 PCLK_VIO_CLK_DIV_SHIFT = 8, 217 PCLK_VIO_CLK_DIV_MASK = 0x1f << PCLK_VIO_CLK_DIV_SHIFT, 218 HCLK_VIO_CLK_DIV_SHIFT = 0, 219 HCLK_VIO_CLK_DIV_MASK = 0x1f << HCLK_VIO_CLK_DIV_SHIFT, 220 221 /* CLKSEL32_CON */ 222 DCLK_VOP_SEL_SHIFT = 7, 223 DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 224 DCLK_VOP_SEL_HDMI = 0, 225 DCLK_VOP_SEL_PLL = 1, 226 DCLK_VOP_PLL_SEL_SHIFT = 6, 227 DCLK_VOP_PLL_SEL_MASK = 1 << DCLK_VOP_PLL_SEL_SHIFT, 228 DCLK_VOP_PLL_SEL_GPLL = 0, 229 DCLK_VOP_PLL_SEL_DPLL = 1, 230 DCLK_VOP_CLK_DIV_SHIFT = 0, 231 DCLK_VOP_CLK_DIV_MASK = 0x3f << DCLK_VOP_CLK_DIV_SHIFT, 232 DCLK_VOP_DIV_CON_WIDTH = 6, 233 234 /* SOFTRST1_CON*/ 235 DDRPHY_SRSTN_CLKDIV_REQ_SHIFT = 0, 236 DDRPHY_SRSTN_CLKDIV_REQ = 1, 237 DDRPHY_SRSTN_CLKDIV_DIS = 0, 238 DDRPHY_SRSTN_CLKDIV_REQ_MASK = 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT, 239 DDRPHY_SRSTN_REQ_SHIFT = 1, 240 DDRPHY_SRSTN_REQ = 1, 241 DDRPHY_SRSTN_DIS = 0, 242 DDRPHY_SRSTN_REQ_MASK = 1 << DDRPHY_SRSTN_REQ_SHIFT, 243 DDRPHY_PSRSTN_REQ_SHIFT = 2, 244 DDRPHY_PSRSTN_REQ = 1, 245 DDRPHY_PSRSTN_DIS = 0, 246 DDRPHY_PSRSTN_REQ_MASK = 1 << DDRPHY_PSRSTN_REQ_SHIFT, 247 248 /* SOFTRST2_CON*/ 249 DDRUPCTL_PSRSTN_REQ_SHIFT = 0, 250 DDRUPCTL_PSRSTN_REQ = 1, 251 DDRUPCTL_PSRSTN_DIS = 0, 252 DDRUPCTL_PSRSTN_REQ_MASK = 1 << DDRUPCTL_PSRSTN_REQ_SHIFT, 253 DDRUPCTL_NSRSTN_REQ_SHIFT = 1, 254 DDRUPCTL_NSRSTN_REQ = 1, 255 DDRUPCTL_NSRSTN_DIS = 0, 256 DDRUPCTL_NSRSTN_REQ_MASK = 1 << DDRUPCTL_NSRSTN_REQ_SHIFT, 257 }; 258 #endif 259