1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __ASM_ARCH_CRU_RK3399_H_ 7 #define __ASM_ARCH_CRU_RK3399_H_ 8 9 #include <common.h> 10 11 /* Private data for the clock driver - used by rockchip_get_cru() */ 12 struct rk3399_clk_priv { 13 struct rk3399_cru *cru; 14 }; 15 16 struct rk3399_pmuclk_priv { 17 struct rk3399_pmucru *pmucru; 18 }; 19 20 struct rk3399_pmucru { 21 u32 ppll_con[6]; 22 u32 reserved[0x1a]; 23 u32 pmucru_clksel[6]; 24 u32 pmucru_clkfrac_con[2]; 25 u32 reserved2[0x18]; 26 u32 pmucru_clkgate_con[3]; 27 u32 reserved3; 28 u32 pmucru_softrst_con[2]; 29 u32 reserved4[2]; 30 u32 pmucru_rstnhold_con[2]; 31 u32 reserved5[2]; 32 u32 pmucru_gatedis_con[2]; 33 }; 34 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); 35 36 struct rk3399_cru { 37 u32 apll_l_con[6]; 38 u32 reserved[2]; 39 u32 apll_b_con[6]; 40 u32 reserved1[2]; 41 u32 dpll_con[6]; 42 u32 reserved2[2]; 43 u32 cpll_con[6]; 44 u32 reserved3[2]; 45 u32 gpll_con[6]; 46 u32 reserved4[2]; 47 u32 npll_con[6]; 48 u32 reserved5[2]; 49 u32 vpll_con[6]; 50 u32 reserved6[0x0a]; 51 u32 clksel_con[108]; 52 u32 reserved7[0x14]; 53 u32 clkgate_con[35]; 54 u32 reserved8[0x1d]; 55 u32 softrst_con[21]; 56 u32 reserved9[0x2b]; 57 u32 glb_srst_fst_value; 58 u32 glb_srst_snd_value; 59 u32 glb_cnt_th; 60 u32 misc_con; 61 u32 glb_rst_con; 62 u32 glb_rst_st; 63 u32 reserved10[0x1a]; 64 u32 sdmmc_con[2]; 65 u32 sdio0_con[2]; 66 u32 sdio1_con[2]; 67 }; 68 check_member(rk3399_cru, sdio1_con[1], 0x594); 69 #define MHz 1000000 70 #define KHz 1000 71 #define OSC_HZ (24*MHz) 72 #define APLL_HZ (600*MHz) 73 #define GPLL_HZ (594*MHz) 74 #define CPLL_HZ (384*MHz) 75 #define PPLL_HZ (676*MHz) 76 77 #define PMU_PCLK_HZ (48*MHz) 78 79 #define ACLKM_CORE_HZ (300*MHz) 80 #define ATCLK_CORE_HZ (300*MHz) 81 #define PCLK_DBG_HZ (100*MHz) 82 83 #define PERIHP_ACLK_HZ (148500*KHz) 84 #define PERIHP_HCLK_HZ (148500*KHz) 85 #define PERIHP_PCLK_HZ (37125*KHz) 86 87 #define PERILP0_ACLK_HZ (99000*KHz) 88 #define PERILP0_HCLK_HZ (99000*KHz) 89 #define PERILP0_PCLK_HZ (49500*KHz) 90 91 #define PERILP1_HCLK_HZ (99000*KHz) 92 #define PERILP1_PCLK_HZ (49500*KHz) 93 94 #define PWM_CLOCK_HZ PMU_PCLK_HZ 95 96 enum apll_l_frequencies { 97 APLL_L_1600_MHZ, 98 APLL_L_600_MHZ, 99 }; 100 101 #endif /* __ASM_ARCH_CRU_RK3399_H_ */ 102