1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ARCH_CRU_RK3328_H_ 8 #define __ASM_ARCH_CRU_RK3328_H_ 9 10 #include <common.h> 11 12 struct rk3328_clk_priv { 13 struct rk3328_cru *cru; 14 ulong rate; 15 }; 16 17 struct rk3328_cru { 18 u32 apll_con[5]; 19 u32 reserved1[3]; 20 u32 dpll_con[5]; 21 u32 reserved2[3]; 22 u32 cpll_con[5]; 23 u32 reserved3[3]; 24 u32 gpll_con[5]; 25 u32 reserved4[3]; 26 u32 mode_con; 27 u32 misc; 28 u32 reserved5[2]; 29 u32 glb_cnt_th; 30 u32 glb_rst_st; 31 u32 glb_srst_snd_value; 32 u32 glb_srst_fst_value; 33 u32 npll_con[5]; 34 u32 reserved6[(0x100 - 0xb4) / 4]; 35 u32 clksel_con[53]; 36 u32 reserved7[(0x200 - 0x1d4) / 4]; 37 u32 clkgate_con[29]; 38 u32 reserved8[3]; 39 u32 ssgtbl[32]; 40 u32 softrst_con[12]; 41 u32 reserved9[(0x380 - 0x330) / 4]; 42 u32 sdmmc_con[2]; 43 u32 sdio_con[2]; 44 u32 emmc_con[2]; 45 u32 sdmmc_ext_con[2]; 46 }; 47 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); 48 #define MHz 1000000 49 #define KHz 1000 50 #define OSC_HZ (24 * MHz) 51 #define APLL_HZ (600 * MHz) 52 #define GPLL_HZ (576 * MHz) 53 #define CPLL_HZ (594 * MHz) 54 55 #define CLK_CORE_HZ (600 * MHz) 56 #define ACLKM_CORE_HZ (300 * MHz) 57 #define PCLK_DBG_HZ (300 * MHz) 58 59 #define PERIHP_ACLK_HZ (144000 * KHz) 60 #define PERIHP_HCLK_HZ (72000 * KHz) 61 #define PERIHP_PCLK_HZ (72000 * KHz) 62 63 #define PWM_CLOCK_HZ (74 * MHz) 64 65 enum apll_frequencies { 66 APLL_816_MHZ, 67 APLL_600_MHZ, 68 }; 69 70 #endif /* __ASM_ARCH_CRU_RK3328_H_ */ 71