1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * (C) Copyright 2008-2014 Rockchip Electronics
5  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 #ifndef _ASM_ARCH_CRU_RK3288_H
10 #define _ASM_ARCH_CRU_RK3288_H
11 
12 #define OSC_HZ		(24 * 1000 * 1000)
13 
14 #define APLL_HZ		(1800 * 1000000)
15 #define GPLL_HZ		(594 * 1000000)
16 #define CPLL_HZ		(384 * 1000000)
17 #define NPLL_HZ		(384 * 1000000)
18 
19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
20 #define PD_BUS_ACLK_HZ	297000000
21 #define PD_BUS_HCLK_HZ	148500000
22 #define PD_BUS_PCLK_HZ	74250000
23 
24 #define PERI_ACLK_HZ	148500000
25 #define PERI_HCLK_HZ	148500000
26 #define PERI_PCLK_HZ	74250000
27 
28 /* Private data for the clock driver - used by rockchip_get_cru() */
29 struct rk3288_clk_priv {
30 	struct rk3288_grf *grf;
31 	struct rk3288_cru *cru;
32 	ulong rate;
33 };
34 
35 struct rk3288_cru {
36 	struct rk3288_pll {
37 		u32 con0;
38 		u32 con1;
39 		u32 con2;
40 		u32 con3;
41 	} pll[5];
42 	u32 cru_mode_con;
43 	u32 reserved0[3];
44 	u32 cru_clksel_con[43];
45 	u32 reserved1[21];
46 	u32 cru_clkgate_con[19];
47 	u32 reserved2;
48 	u32 cru_glb_srst_fst_value;
49 	u32 cru_glb_srst_snd_value;
50 	u32 cru_softrst_con[12];
51 	u32 cru_misc_con;
52 	u32 cru_glb_cnt_th;
53 	u32 cru_glb_rst_con;
54 	u32 reserved3;
55 	u32 cru_glb_rst_st;
56 	u32 reserved4;
57 	u32 cru_sdmmc_con[2];
58 	u32 cru_sdio0_con[2];
59 	u32 cru_sdio1_con[2];
60 	u32 cru_emmc_con[2];
61 };
62 check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
63 
64 /* CRU_CLKSEL11_CON */
65 enum {
66 	HSICPHY_DIV_SHIFT	= 8,
67 	HSICPHY_DIV_MASK	= 0x3f << HSICPHY_DIV_SHIFT,
68 
69 	MMC0_PLL_SHIFT		= 6,
70 	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
71 	MMC0_PLL_SELECT_CODEC	= 0,
72 	MMC0_PLL_SELECT_GENERAL,
73 	MMC0_PLL_SELECT_24MHZ,
74 
75 	MMC0_DIV_SHIFT		= 0,
76 	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
77 };
78 
79 /* CRU_CLKSEL12_CON */
80 enum {
81 	EMMC_PLL_SHIFT		= 0xe,
82 	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
83 	EMMC_PLL_SELECT_CODEC	= 0,
84 	EMMC_PLL_SELECT_GENERAL,
85 	EMMC_PLL_SELECT_24MHZ,
86 
87 	EMMC_DIV_SHIFT		= 8,
88 	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
89 
90 	SDIO0_PLL_SHIFT		= 6,
91 	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,
92 	SDIO0_PLL_SELECT_CODEC	= 0,
93 	SDIO0_PLL_SELECT_GENERAL,
94 	SDIO0_PLL_SELECT_24MHZ,
95 
96 	SDIO0_DIV_SHIFT		= 0,
97 	SDIO0_DIV_MASK		= 0x3f << SDIO0_DIV_SHIFT,
98 };
99 
100 /* CRU_CLKSEL21_CON */
101 enum {
102 	MAC_DIV_CON_SHIFT	= 0xf,
103 	MAC_DIV_CON_MASK	= 0x1f << MAC_DIV_CON_SHIFT,
104 
105 	RMII_EXTCLK_SHIFT	= 4,
106 	RMII_EXTCLK_MASK	= 1 << RMII_EXTCLK_SHIFT,
107 	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
108 	RMII_EXTCLK_SELECT_EXT_CLK = 1,
109 
110 	EMAC_PLL_SHIFT		= 0,
111 	EMAC_PLL_MASK		= 0x3 << EMAC_PLL_SHIFT,
112 	EMAC_PLL_SELECT_NEW	= 0x0,
113 	EMAC_PLL_SELECT_CODEC	= 0x1,
114 	EMAC_PLL_SELECT_GENERAL	= 0x2,
115 };
116 
117 /* CRU_CLKSEL25_CON */
118 enum {
119 	SPI1_PLL_SHIFT		= 0xf,
120 	SPI1_PLL_MASK		= 1 << SPI1_PLL_SHIFT,
121 	SPI1_PLL_SELECT_CODEC	= 0,
122 	SPI1_PLL_SELECT_GENERAL,
123 
124 	SPI1_DIV_SHIFT		= 8,
125 	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
126 
127 	SPI0_PLL_SHIFT		= 7,
128 	SPI0_PLL_MASK		= 1 << SPI0_PLL_SHIFT,
129 	SPI0_PLL_SELECT_CODEC	= 0,
130 	SPI0_PLL_SELECT_GENERAL,
131 
132 	SPI0_DIV_SHIFT		= 0,
133 	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
134 };
135 
136 /* CRU_CLKSEL37_CON */
137 enum {
138 	PCLK_CORE_DBG_DIV_SHIFT	= 9,
139 	PCLK_CORE_DBG_DIV_MASK	= 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
140 
141 	ATCLK_CORE_DIV_CON_SHIFT = 4,
142 	ATCLK_CORE_DIV_CON_MASK	= 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
143 
144 	CLK_L2RAM_DIV_SHIFT	= 0,
145 	CLK_L2RAM_DIV_MASK	= 7 << CLK_L2RAM_DIV_SHIFT,
146 };
147 
148 /* CRU_CLKSEL39_CON */
149 enum {
150 	ACLK_HEVC_PLL_SHIFT	= 0xe,
151 	ACLK_HEVC_PLL_MASK	= 3 << ACLK_HEVC_PLL_SHIFT,
152 	ACLK_HEVC_PLL_SELECT_CODEC = 0,
153 	ACLK_HEVC_PLL_SELECT_GENERAL,
154 	ACLK_HEVC_PLL_SELECT_NEW,
155 
156 	ACLK_HEVC_DIV_SHIFT	= 8,
157 	ACLK_HEVC_DIV_MASK	= 0x1f << ACLK_HEVC_DIV_SHIFT,
158 
159 	SPI2_PLL_SHIFT		= 7,
160 	SPI2_PLL_MASK		= 1 << SPI2_PLL_SHIFT,
161 	SPI2_PLL_SELECT_CODEC	= 0,
162 	SPI2_PLL_SELECT_GENERAL,
163 
164 	SPI2_DIV_SHIFT		= 0,
165 	SPI2_DIV_MASK		= 0x7f << SPI2_DIV_SHIFT,
166 };
167 
168 /* CRU_MODE_CON */
169 enum {
170 	CRU_MODE_MASK		= 3,
171 
172 	NPLL_MODE_SHIFT		= 0xe,
173 	NPLL_MODE_MASK		= CRU_MODE_MASK << NPLL_MODE_SHIFT,
174 	NPLL_MODE_SLOW		= 0,
175 	NPLL_MODE_NORMAL,
176 	NPLL_MODE_DEEP,
177 
178 	GPLL_MODE_SHIFT		= 0xc,
179 	GPLL_MODE_MASK		= CRU_MODE_MASK << GPLL_MODE_SHIFT,
180 	GPLL_MODE_SLOW		= 0,
181 	GPLL_MODE_NORMAL,
182 	GPLL_MODE_DEEP,
183 
184 	CPLL_MODE_SHIFT		= 8,
185 	CPLL_MODE_MASK		= CRU_MODE_MASK << CPLL_MODE_SHIFT,
186 	CPLL_MODE_SLOW		= 0,
187 	CPLL_MODE_NORMAL,
188 	CPLL_MODE_DEEP,
189 
190 	DPLL_MODE_SHIFT		= 4,
191 	DPLL_MODE_MASK		= CRU_MODE_MASK << DPLL_MODE_SHIFT,
192 	DPLL_MODE_SLOW		= 0,
193 	DPLL_MODE_NORMAL,
194 	DPLL_MODE_DEEP,
195 
196 	APLL_MODE_SHIFT		= 0,
197 	APLL_MODE_MASK		= CRU_MODE_MASK << APLL_MODE_SHIFT,
198 	APLL_MODE_SLOW		= 0,
199 	APLL_MODE_NORMAL,
200 	APLL_MODE_DEEP,
201 };
202 
203 /* CRU_APLL_CON0 */
204 enum {
205 	CLKR_SHIFT		= 8,
206 	CLKR_MASK		= 0x3f << CLKR_SHIFT,
207 
208 	CLKOD_SHIFT		= 0,
209 	CLKOD_MASK		= 0xf << CLKOD_SHIFT,
210 };
211 
212 /* CRU_APLL_CON1 */
213 enum {
214 	LOCK_SHIFT		= 0x1f,
215 	LOCK_MASK		= 1 << LOCK_SHIFT,
216 	LOCK_UNLOCK		= 0,
217 	LOCK_LOCK,
218 
219 	CLKF_SHIFT		= 0,
220 	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
221 };
222 
223 /* CRU_GLB_RST_ST */
224 enum {
225 	GLB_POR_RST,
226 	FST_GLB_RST_ST		= BIT(0),
227 	SND_GLB_RST_ST		= BIT(1),
228 	FST_GLB_TSADC_RST_ST	= BIT(2),
229 	SND_GLB_TSADC_RST_ST	= BIT(3),
230 	FST_GLB_WDT_RST_ST	= BIT(4),
231 	SND_GLB_WDT_RST_ST	= BIT(5),
232 	GLB_RST_ST_MASK		= GENMASK(5, 0),
233 };
234 
235 #endif
236