1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * (C) Copyright 2008-2014 Rockchip Electronics 5 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef _ASM_ARCH_CRU_RK3288_H 10 #define _ASM_ARCH_CRU_RK3288_H 11 12 #define OSC_HZ (24 * 1000 * 1000) 13 14 #define APLL_HZ (1800 * 1000000) 15 #define GPLL_HZ (594 * 1000000) 16 #define CPLL_HZ (384 * 1000000) 17 #define NPLL_HZ (384 * 1000000) 18 19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ 20 #define PD_BUS_ACLK_HZ 297000000 21 #define PD_BUS_HCLK_HZ 148500000 22 #define PD_BUS_PCLK_HZ 74250000 23 24 #define PERI_ACLK_HZ 148500000 25 #define PERI_HCLK_HZ 148500000 26 #define PERI_PCLK_HZ 74250000 27 28 struct rk3288_cru { 29 struct rk3288_pll { 30 u32 con0; 31 u32 con1; 32 u32 con2; 33 u32 con3; 34 } pll[5]; 35 u32 cru_mode_con; 36 u32 reserved0[3]; 37 u32 cru_clksel_con[43]; 38 u32 reserved1[21]; 39 u32 cru_clkgate_con[19]; 40 u32 reserved2; 41 u32 cru_glb_srst_fst_value; 42 u32 cru_glb_srst_snd_value; 43 u32 cru_softrst_con[12]; 44 u32 cru_misc_con; 45 u32 cru_glb_cnt_th; 46 u32 cru_glb_rst_con; 47 u32 reserved3; 48 u32 cru_glb_rst_st; 49 u32 reserved4; 50 u32 cru_sdmmc_con[2]; 51 u32 cru_sdio0_con[2]; 52 u32 cru_sdio1_con[2]; 53 u32 cru_emmc_con[2]; 54 }; 55 check_member(rk3288_cru, cru_emmc_con[1], 0x021c); 56 57 /* CRU_CLKSEL11_CON */ 58 enum { 59 HSICPHY_DIV_SHIFT = 8, 60 HSICPHY_DIV_MASK = 0x3f, 61 62 MMC0_PLL_SHIFT = 6, 63 MMC0_PLL_MASK = 3, 64 MMC0_PLL_SELECT_CODEC = 0, 65 MMC0_PLL_SELECT_GENERAL, 66 MMC0_PLL_SELECT_24MHZ, 67 68 MMC0_DIV_SHIFT = 0, 69 MMC0_DIV_MASK = 0x3f, 70 }; 71 72 /* CRU_CLKSEL12_CON */ 73 enum { 74 EMMC_PLL_SHIFT = 0xe, 75 EMMC_PLL_MASK = 3, 76 EMMC_PLL_SELECT_CODEC = 0, 77 EMMC_PLL_SELECT_GENERAL, 78 EMMC_PLL_SELECT_24MHZ, 79 80 EMMC_DIV_SHIFT = 8, 81 EMMC_DIV_MASK = 0x3f, 82 83 SDIO0_PLL_SHIFT = 6, 84 SDIO0_PLL_MASK = 3, 85 SDIO0_PLL_SELECT_CODEC = 0, 86 SDIO0_PLL_SELECT_GENERAL, 87 SDIO0_PLL_SELECT_24MHZ, 88 89 SDIO0_DIV_SHIFT = 0, 90 SDIO0_DIV_MASK = 0x3f, 91 }; 92 93 /* CRU_CLKSEL25_CON */ 94 enum { 95 SPI1_PLL_SHIFT = 0xf, 96 SPI1_PLL_MASK = 1, 97 SPI1_PLL_SELECT_CODEC = 0, 98 SPI1_PLL_SELECT_GENERAL, 99 100 SPI1_DIV_SHIFT = 8, 101 SPI1_DIV_MASK = 0x7f, 102 103 SPI0_PLL_SHIFT = 7, 104 SPI0_PLL_MASK = 1, 105 SPI0_PLL_SELECT_CODEC = 0, 106 SPI0_PLL_SELECT_GENERAL, 107 108 SPI0_DIV_SHIFT = 0, 109 SPI0_DIV_MASK = 0x7f, 110 }; 111 112 /* CRU_CLKSEL37_CON */ 113 enum { 114 PCLK_CORE_DBG_DIV_SHIFT = 9, 115 PCLK_CORE_DBG_DIV_MASK = 0x1f, 116 117 ATCLK_CORE_DIV_CON_SHIFT = 4, 118 ATCLK_CORE_DIV_CON_MASK = 0x1f, 119 120 CLK_L2RAM_DIV_SHIFT = 0, 121 CLK_L2RAM_DIV_MASK = 7, 122 }; 123 124 /* CRU_CLKSEL39_CON */ 125 enum { 126 ACLK_HEVC_PLL_SHIFT = 0xe, 127 ACLK_HEVC_PLL_MASK = 3, 128 ACLK_HEVC_PLL_SELECT_CODEC = 0, 129 ACLK_HEVC_PLL_SELECT_GENERAL, 130 ACLK_HEVC_PLL_SELECT_NEW, 131 132 ACLK_HEVC_DIV_SHIFT = 8, 133 ACLK_HEVC_DIV_MASK = 0x1f, 134 135 SPI2_PLL_SHIFT = 7, 136 SPI2_PLL_MASK = 1, 137 SPI2_PLL_SELECT_CODEC = 0, 138 SPI2_PLL_SELECT_GENERAL, 139 140 SPI2_DIV_SHIFT = 0, 141 SPI2_DIV_MASK = 0x7f, 142 }; 143 144 /* CRU_MODE_CON */ 145 enum { 146 NPLL_MODE_SHIFT = 0xe, 147 NPLL_MODE_MASK = 3, 148 NPLL_MODE_SLOW = 0, 149 NPLL_MODE_NORMAL, 150 NPLL_MODE_DEEP, 151 152 GPLL_MODE_SHIFT = 0xc, 153 GPLL_MODE_MASK = 3, 154 GPLL_MODE_SLOW = 0, 155 GPLL_MODE_NORMAL, 156 GPLL_MODE_DEEP, 157 158 CPLL_MODE_SHIFT = 8, 159 CPLL_MODE_MASK = 3, 160 CPLL_MODE_SLOW = 0, 161 CPLL_MODE_NORMAL, 162 CPLL_MODE_DEEP, 163 164 DPLL_MODE_SHIFT = 4, 165 DPLL_MODE_MASK = 3, 166 DPLL_MODE_SLOW = 0, 167 DPLL_MODE_NORMAL, 168 DPLL_MODE_DEEP, 169 170 APLL_MODE_SHIFT = 0, 171 APLL_MODE_MASK = 3, 172 APLL_MODE_SLOW = 0, 173 APLL_MODE_NORMAL, 174 APLL_MODE_DEEP, 175 }; 176 177 /* CRU_APLL_CON0 */ 178 enum { 179 CLKR_SHIFT = 8, 180 CLKR_MASK = 0x3f, 181 182 CLKOD_SHIFT = 0, 183 CLKOD_MASK = 0xf, 184 }; 185 186 /* CRU_APLL_CON1 */ 187 enum { 188 LOCK_SHIFT = 0x1f, 189 LOCK_MASK = 1, 190 LOCK_UNLOCK = 0, 191 LOCK_LOCK, 192 193 CLKF_SHIFT = 0, 194 CLKF_MASK = 0x1fff, 195 }; 196 197 #endif 198