1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * (C) Copyright 2008-2014 Rockchip Electronics 5 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef _ASM_ARCH_CRU_RK3288_H 10 #define _ASM_ARCH_CRU_RK3288_H 11 12 #define OSC_HZ (24 * 1000 * 1000) 13 14 #define APLL_HZ (1800 * 1000000) 15 #define GPLL_HZ (594 * 1000000) 16 #define CPLL_HZ (384 * 1000000) 17 #define NPLL_HZ (384 * 1000000) 18 19 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */ 20 #define PD_BUS_ACLK_HZ 297000000 21 #define PD_BUS_HCLK_HZ 148500000 22 #define PD_BUS_PCLK_HZ 74250000 23 24 #define PERI_ACLK_HZ 148500000 25 #define PERI_HCLK_HZ 148500000 26 #define PERI_PCLK_HZ 74250000 27 28 struct rk3288_cru { 29 struct rk3288_pll { 30 u32 con0; 31 u32 con1; 32 u32 con2; 33 u32 con3; 34 } pll[5]; 35 u32 cru_mode_con; 36 u32 reserved0[3]; 37 u32 cru_clksel_con[43]; 38 u32 reserved1[21]; 39 u32 cru_clkgate_con[19]; 40 u32 reserved2; 41 u32 cru_glb_srst_fst_value; 42 u32 cru_glb_srst_snd_value; 43 u32 cru_softrst_con[12]; 44 u32 cru_misc_con; 45 u32 cru_glb_cnt_th; 46 u32 cru_glb_rst_con; 47 u32 reserved3; 48 u32 cru_glb_rst_st; 49 u32 reserved4; 50 u32 cru_sdmmc_con[2]; 51 u32 cru_sdio0_con[2]; 52 u32 cru_sdio1_con[2]; 53 u32 cru_emmc_con[2]; 54 }; 55 check_member(rk3288_cru, cru_emmc_con[1], 0x021c); 56 57 /* CRU_CLKSEL11_CON */ 58 enum { 59 HSICPHY_DIV_SHIFT = 8, 60 HSICPHY_DIV_MASK = 0x3f, 61 62 MMC0_PLL_SHIFT = 6, 63 MMC0_PLL_MASK = 3, 64 MMC0_PLL_SELECT_CODEC = 0, 65 MMC0_PLL_SELECT_GENERAL, 66 MMC0_PLL_SELECT_24MHZ, 67 68 MMC0_DIV_SHIFT = 0, 69 MMC0_DIV_MASK = 0x3f, 70 }; 71 72 /* CRU_CLKSEL12_CON */ 73 enum { 74 EMMC_PLL_SHIFT = 0xe, 75 EMMC_PLL_MASK = 3, 76 EMMC_PLL_SELECT_CODEC = 0, 77 EMMC_PLL_SELECT_GENERAL, 78 EMMC_PLL_SELECT_24MHZ, 79 80 EMMC_DIV_SHIFT = 8, 81 EMMC_DIV_MASK = 0x3f, 82 83 SDIO0_PLL_SHIFT = 6, 84 SDIO0_PLL_MASK = 3, 85 SDIO0_PLL_SELECT_CODEC = 0, 86 SDIO0_PLL_SELECT_GENERAL, 87 SDIO0_PLL_SELECT_24MHZ, 88 89 SDIO0_DIV_SHIFT = 0, 90 SDIO0_DIV_MASK = 0x3f, 91 }; 92 93 /* CRU_CLKSEL21_CON */ 94 enum { 95 MAC_DIV_CON_SHIFT = 0xf, 96 MAC_DIV_CON_MASK = 0x1f, 97 98 RMII_EXTCLK_SHIFT = 4, 99 RMII_EXTCLK_MASK = 1, 100 RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, 101 RMII_EXTCLK_SELECT_EXT_CLK = 1, 102 103 EMAC_PLL_SHIFT = 0, 104 EMAC_PLL_MASK = 0x3, 105 EMAC_PLL_SELECT_NEW = 0x0, 106 EMAC_PLL_SELECT_CODEC = 0x1, 107 EMAC_PLL_SELECT_GENERAL = 0x2, 108 }; 109 110 /* CRU_CLKSEL25_CON */ 111 enum { 112 SPI1_PLL_SHIFT = 0xf, 113 SPI1_PLL_MASK = 1, 114 SPI1_PLL_SELECT_CODEC = 0, 115 SPI1_PLL_SELECT_GENERAL, 116 117 SPI1_DIV_SHIFT = 8, 118 SPI1_DIV_MASK = 0x7f, 119 120 SPI0_PLL_SHIFT = 7, 121 SPI0_PLL_MASK = 1, 122 SPI0_PLL_SELECT_CODEC = 0, 123 SPI0_PLL_SELECT_GENERAL, 124 125 SPI0_DIV_SHIFT = 0, 126 SPI0_DIV_MASK = 0x7f, 127 }; 128 129 /* CRU_CLKSEL37_CON */ 130 enum { 131 PCLK_CORE_DBG_DIV_SHIFT = 9, 132 PCLK_CORE_DBG_DIV_MASK = 0x1f, 133 134 ATCLK_CORE_DIV_CON_SHIFT = 4, 135 ATCLK_CORE_DIV_CON_MASK = 0x1f, 136 137 CLK_L2RAM_DIV_SHIFT = 0, 138 CLK_L2RAM_DIV_MASK = 7, 139 }; 140 141 /* CRU_CLKSEL39_CON */ 142 enum { 143 ACLK_HEVC_PLL_SHIFT = 0xe, 144 ACLK_HEVC_PLL_MASK = 3, 145 ACLK_HEVC_PLL_SELECT_CODEC = 0, 146 ACLK_HEVC_PLL_SELECT_GENERAL, 147 ACLK_HEVC_PLL_SELECT_NEW, 148 149 ACLK_HEVC_DIV_SHIFT = 8, 150 ACLK_HEVC_DIV_MASK = 0x1f, 151 152 SPI2_PLL_SHIFT = 7, 153 SPI2_PLL_MASK = 1, 154 SPI2_PLL_SELECT_CODEC = 0, 155 SPI2_PLL_SELECT_GENERAL, 156 157 SPI2_DIV_SHIFT = 0, 158 SPI2_DIV_MASK = 0x7f, 159 }; 160 161 /* CRU_MODE_CON */ 162 enum { 163 NPLL_MODE_SHIFT = 0xe, 164 NPLL_MODE_MASK = 3, 165 NPLL_MODE_SLOW = 0, 166 NPLL_MODE_NORMAL, 167 NPLL_MODE_DEEP, 168 169 GPLL_MODE_SHIFT = 0xc, 170 GPLL_MODE_MASK = 3, 171 GPLL_MODE_SLOW = 0, 172 GPLL_MODE_NORMAL, 173 GPLL_MODE_DEEP, 174 175 CPLL_MODE_SHIFT = 8, 176 CPLL_MODE_MASK = 3, 177 CPLL_MODE_SLOW = 0, 178 CPLL_MODE_NORMAL, 179 CPLL_MODE_DEEP, 180 181 DPLL_MODE_SHIFT = 4, 182 DPLL_MODE_MASK = 3, 183 DPLL_MODE_SLOW = 0, 184 DPLL_MODE_NORMAL, 185 DPLL_MODE_DEEP, 186 187 APLL_MODE_SHIFT = 0, 188 APLL_MODE_MASK = 3, 189 APLL_MODE_SLOW = 0, 190 APLL_MODE_NORMAL, 191 APLL_MODE_DEEP, 192 }; 193 194 /* CRU_APLL_CON0 */ 195 enum { 196 CLKR_SHIFT = 8, 197 CLKR_MASK = 0x3f, 198 199 CLKOD_SHIFT = 0, 200 CLKOD_MASK = 0xf, 201 }; 202 203 /* CRU_APLL_CON1 */ 204 enum { 205 LOCK_SHIFT = 0x1f, 206 LOCK_MASK = 1, 207 LOCK_UNLOCK = 0, 208 LOCK_LOCK, 209 210 CLKF_SHIFT = 0, 211 CLKF_MASK = 0x1fff, 212 }; 213 214 #endif 215