1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4  */
5 #ifndef _ASM_ARCH_CRU_RK322X_H
6 #define _ASM_ARCH_CRU_RK322X_H
7 
8 #include <common.h>
9 
10 #define MHz		1000000
11 #define OSC_HZ		(24 * MHz)
12 
13 #define APLL_HZ		(600 * MHz)
14 #define GPLL_HZ		(594 * MHz)
15 
16 #define CORE_PERI_HZ	150000000
17 #define CORE_ACLK_HZ	300000000
18 
19 #define BUS_ACLK_HZ	148500000
20 #define BUS_HCLK_HZ	148500000
21 #define BUS_PCLK_HZ	74250000
22 
23 #define PERI_ACLK_HZ	148500000
24 #define PERI_HCLK_HZ	148500000
25 #define PERI_PCLK_HZ	74250000
26 
27 /* Private data for the clock driver - used by rockchip_get_cru() */
28 struct rk322x_clk_priv {
29 	struct rk322x_cru *cru;
30 	ulong rate;
31 };
32 
33 struct rk322x_cru {
34 	struct rk322x_pll {
35 		unsigned int con0;
36 		unsigned int con1;
37 		unsigned int con2;
38 	} pll[4];
39 	unsigned int reserved0[4];
40 	unsigned int cru_mode_con;
41 	unsigned int cru_clksel_con[35];
42 	unsigned int cru_clkgate_con[16];
43 	unsigned int cru_softrst_con[9];
44 	unsigned int cru_misc_con;
45 	unsigned int reserved1[2];
46 	unsigned int cru_glb_cnt_th;
47 	unsigned int reserved2[3];
48 	unsigned int cru_glb_rst_st;
49 	unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
50 	unsigned int cru_sdmmc_con[2];
51 	unsigned int cru_sdio_con[2];
52 	unsigned int reserved4[2];
53 	unsigned int cru_emmc_con[2];
54 	unsigned int reserved5[4];
55 	unsigned int cru_glb_srst_fst_value;
56 	unsigned int cru_glb_srst_snd_value;
57 	unsigned int cru_pll_mask_con;
58 };
59 check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
60 
61 struct pll_div {
62 	u32 refdiv;
63 	u32 fbdiv;
64 	u32 postdiv1;
65 	u32 postdiv2;
66 	u32 frac;
67 };
68 
69 enum {
70 	/* PLLCON0*/
71 	PLL_BP_SHIFT		= 15,
72 	PLL_POSTDIV1_SHIFT	= 12,
73 	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
74 	PLL_FBDIV_SHIFT		= 0,
75 	PLL_FBDIV_MASK		= 0xfff,
76 
77 	/* PLLCON1 */
78 	PLL_RST_SHIFT		= 14,
79 	PLL_PD_SHIFT		= 13,
80 	PLL_PD_MASK		= 1 << PLL_PD_SHIFT,
81 	PLL_DSMPD_SHIFT		= 12,
82 	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
83 	PLL_LOCK_STATUS_SHIFT	= 10,
84 	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
85 	PLL_POSTDIV2_SHIFT	= 6,
86 	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
87 	PLL_REFDIV_SHIFT	= 0,
88 	PLL_REFDIV_MASK		= 0x3f,
89 
90 	/* CRU_MODE */
91 	GPLL_MODE_SHIFT		= 12,
92 	GPLL_MODE_MASK		= 1 << GPLL_MODE_SHIFT,
93 	GPLL_MODE_SLOW		= 0,
94 	GPLL_MODE_NORM,
95 	CPLL_MODE_SHIFT		= 8,
96 	CPLL_MODE_MASK		= 1 << CPLL_MODE_SHIFT,
97 	CPLL_MODE_SLOW		= 0,
98 	CPLL_MODE_NORM,
99 	DPLL_MODE_SHIFT		= 4,
100 	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
101 	DPLL_MODE_SLOW		= 0,
102 	DPLL_MODE_NORM,
103 	APLL_MODE_SHIFT		= 0,
104 	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
105 	APLL_MODE_SLOW		= 0,
106 	APLL_MODE_NORM,
107 
108 	/* CRU_CLK_SEL0_CON */
109 	BUS_ACLK_PLL_SEL_SHIFT	= 13,
110 	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
111 	BUS_ACLK_PLL_SEL_APLL	= 0,
112 	BUS_ACLK_PLL_SEL_GPLL,
113 	BUS_ACLK_PLL_SEL_HDMIPLL,
114 	BUS_ACLK_DIV_SHIFT	= 8,
115 	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
116 	CORE_CLK_PLL_SEL_SHIFT	= 6,
117 	CORE_CLK_PLL_SEL_MASK	= 3 << CORE_CLK_PLL_SEL_SHIFT,
118 	CORE_CLK_PLL_SEL_APLL	= 0,
119 	CORE_CLK_PLL_SEL_GPLL,
120 	CORE_CLK_PLL_SEL_DPLL,
121 	CORE_DIV_CON_SHIFT	= 0,
122 	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
123 
124 	/* CRU_CLK_SEL1_CON */
125 	BUS_PCLK_DIV_SHIFT	= 12,
126 	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
127 	BUS_HCLK_DIV_SHIFT	= 8,
128 	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
129 	CORE_ACLK_DIV_SHIFT	= 4,
130 	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
131 	CORE_PERI_DIV_SHIFT	= 0,
132 	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
133 
134 	/* CRU_CLKSEL5_CON */
135 	GMAC_OUT_PLL_SHIFT	= 15,
136 	GMAC_OUT_PLL_MASK	= 1 << GMAC_OUT_PLL_SHIFT,
137 	GMAC_OUT_DIV_SHIFT	= 8,
138 	GMAC_OUT_DIV_MASK	= 0x1f << GMAC_OUT_DIV_SHIFT,
139 	MAC_PLL_SEL_SHIFT	= 7,
140 	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
141 	RMII_EXTCLK_SLE_SHIFT	= 5,
142 	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SLE_SHIFT,
143 	RMII_EXTCLK_SEL_INT		= 0,
144 	RMII_EXTCLK_SEL_EXT,
145 	CLK_MAC_DIV_SHIFT	= 0,
146 	CLK_MAC_DIV_MASK	= 0x1f << CLK_MAC_DIV_SHIFT,
147 
148 	/* CRU_CLKSEL10_CON */
149 	PERI_PCLK_DIV_SHIFT	= 12,
150 	PERI_PCLK_DIV_MASK	= 7 << PERI_PCLK_DIV_SHIFT,
151 	PERI_PLL_SEL_SHIFT	= 10,
152 	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
153 	PERI_PLL_CPLL		= 0,
154 	PERI_PLL_GPLL,
155 	PERI_PLL_HDMIPLL,
156 	PERI_HCLK_DIV_SHIFT	= 8,
157 	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
158 	PERI_ACLK_DIV_SHIFT	= 0,
159 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
160 
161 	/* CRU_CLKSEL11_CON */
162 	EMMC_PLL_SHIFT		= 12,
163 	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
164 	EMMC_SEL_CPLL		= 0,
165 	EMMC_SEL_GPLL,
166 	EMMC_SEL_24M,
167 	SDIO_PLL_SHIFT		= 10,
168 	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
169 	SDIO_SEL_CPLL		= 0,
170 	SDIO_SEL_GPLL,
171 	SDIO_SEL_24M,
172 	MMC0_PLL_SHIFT		= 8,
173 	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
174 	MMC0_SEL_CPLL		= 0,
175 	MMC0_SEL_GPLL,
176 	MMC0_SEL_24M,
177 	MMC0_DIV_SHIFT		= 0,
178 	MMC0_DIV_MASK		= 0xff << MMC0_DIV_SHIFT,
179 
180 	/* CRU_CLKSEL12_CON */
181 	EMMC_DIV_SHIFT		= 8,
182 	EMMC_DIV_MASK		= 0xff << EMMC_DIV_SHIFT,
183 	SDIO_DIV_SHIFT		= 0,
184 	SDIO_DIV_MASK		= 0xff << SDIO_DIV_SHIFT,
185 
186 	/* CRU_CLKSEL26_CON */
187 	DDR_CLK_PLL_SEL_SHIFT	= 8,
188 	DDR_CLK_PLL_SEL_MASK	= 3 << DDR_CLK_PLL_SEL_SHIFT,
189 	DDR_CLK_SEL_DPLL	= 0,
190 	DDR_CLK_SEL_GPLL,
191 	DDR_CLK_SEL_APLL,
192 	DDR_DIV_SEL_SHIFT	= 0,
193 	DDR_DIV_SEL_MASK	= 3 << DDR_DIV_SEL_SHIFT,
194 
195 	/* CRU_CLKSEL27_CON */
196 	VOP_DCLK_DIV_SHIFT	= 8,
197 	VOP_DCLK_DIV_MASK	= 0xff << VOP_DCLK_DIV_SHIFT,
198 	VOP_PLL_SEL_SHIFT	= 1,
199 	VOP_PLL_SEL_MASK	= 1 << VOP_PLL_SEL_SHIFT,
200 
201 	/* CRU_CLKSEL29_CON */
202 	GMAC_CLK_SRC_SHIFT	= 12,
203 	GMAC_CLK_SRC_MASK	= 1 << GMAC_CLK_SRC_SHIFT,
204 
205 	/* CRU_SOFTRST5_CON */
206 	DDRCTRL_PSRST_SHIFT	= 11,
207 	DDRCTRL_SRST_SHIFT	= 10,
208 	DDRPHY_PSRST_SHIFT	= 9,
209 	DDRPHY_SRST_SHIFT	= 8,
210 };
211 #endif
212