1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef _ASM_ARCH_CRU_RK322X_H 7 #define _ASM_ARCH_CRU_RK322X_H 8 9 #include <common.h> 10 11 #define MHz 1000000 12 #define OSC_HZ (24 * MHz) 13 14 #define APLL_HZ (600 * MHz) 15 #define GPLL_HZ (594 * MHz) 16 17 #define CORE_PERI_HZ 150000000 18 #define CORE_ACLK_HZ 300000000 19 20 #define BUS_ACLK_HZ 148500000 21 #define BUS_HCLK_HZ 148500000 22 #define BUS_PCLK_HZ 74250000 23 24 #define PERI_ACLK_HZ 148500000 25 #define PERI_HCLK_HZ 148500000 26 #define PERI_PCLK_HZ 74250000 27 28 /* Private data for the clock driver - used by rockchip_get_cru() */ 29 struct rk322x_clk_priv { 30 struct rk322x_cru *cru; 31 ulong rate; 32 }; 33 34 struct rk322x_cru { 35 struct rk322x_pll { 36 unsigned int con0; 37 unsigned int con1; 38 unsigned int con2; 39 } pll[4]; 40 unsigned int reserved0[4]; 41 unsigned int cru_mode_con; 42 unsigned int cru_clksel_con[35]; 43 unsigned int cru_clkgate_con[16]; 44 unsigned int cru_softrst_con[9]; 45 unsigned int cru_misc_con; 46 unsigned int reserved1[2]; 47 unsigned int cru_glb_cnt_th; 48 unsigned int reserved2[3]; 49 unsigned int cru_glb_rst_st; 50 unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; 51 unsigned int cru_sdmmc_con[2]; 52 unsigned int cru_sdio_con[2]; 53 unsigned int reserved4[2]; 54 unsigned int cru_emmc_con[2]; 55 unsigned int reserved5[4]; 56 unsigned int cru_glb_srst_fst_value; 57 unsigned int cru_glb_srst_snd_value; 58 unsigned int cru_pll_mask_con; 59 }; 60 check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); 61 62 struct pll_div { 63 u32 refdiv; 64 u32 fbdiv; 65 u32 postdiv1; 66 u32 postdiv2; 67 u32 frac; 68 }; 69 70 enum { 71 /* PLLCON0*/ 72 PLL_BP_SHIFT = 15, 73 PLL_POSTDIV1_SHIFT = 12, 74 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, 75 PLL_FBDIV_SHIFT = 0, 76 PLL_FBDIV_MASK = 0xfff, 77 78 /* PLLCON1 */ 79 PLL_RST_SHIFT = 14, 80 PLL_PD_SHIFT = 13, 81 PLL_PD_MASK = 1 << PLL_PD_SHIFT, 82 PLL_DSMPD_SHIFT = 12, 83 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 84 PLL_LOCK_STATUS_SHIFT = 10, 85 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 86 PLL_POSTDIV2_SHIFT = 6, 87 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, 88 PLL_REFDIV_SHIFT = 0, 89 PLL_REFDIV_MASK = 0x3f, 90 91 /* CRU_MODE */ 92 GPLL_MODE_SHIFT = 12, 93 GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, 94 GPLL_MODE_SLOW = 0, 95 GPLL_MODE_NORM, 96 CPLL_MODE_SHIFT = 8, 97 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, 98 CPLL_MODE_SLOW = 0, 99 CPLL_MODE_NORM, 100 DPLL_MODE_SHIFT = 4, 101 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, 102 DPLL_MODE_SLOW = 0, 103 DPLL_MODE_NORM, 104 APLL_MODE_SHIFT = 0, 105 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, 106 APLL_MODE_SLOW = 0, 107 APLL_MODE_NORM, 108 109 /* CRU_CLK_SEL0_CON */ 110 BUS_ACLK_PLL_SEL_SHIFT = 13, 111 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, 112 BUS_ACLK_PLL_SEL_APLL = 0, 113 BUS_ACLK_PLL_SEL_GPLL, 114 BUS_ACLK_PLL_SEL_HDMIPLL, 115 BUS_ACLK_DIV_SHIFT = 8, 116 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, 117 CORE_CLK_PLL_SEL_SHIFT = 6, 118 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 119 CORE_CLK_PLL_SEL_APLL = 0, 120 CORE_CLK_PLL_SEL_GPLL, 121 CORE_CLK_PLL_SEL_DPLL, 122 CORE_DIV_CON_SHIFT = 0, 123 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 124 125 /* CRU_CLK_SEL1_CON */ 126 BUS_PCLK_DIV_SHIFT = 12, 127 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, 128 BUS_HCLK_DIV_SHIFT = 8, 129 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, 130 CORE_ACLK_DIV_SHIFT = 4, 131 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, 132 CORE_PERI_DIV_SHIFT = 0, 133 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, 134 135 /* CRU_CLKSEL5_CON */ 136 GMAC_OUT_PLL_SHIFT = 15, 137 GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, 138 GMAC_OUT_DIV_SHIFT = 8, 139 GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, 140 MAC_PLL_SEL_SHIFT = 7, 141 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, 142 RMII_EXTCLK_SLE_SHIFT = 5, 143 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, 144 RMII_EXTCLK_SEL_INT = 0, 145 RMII_EXTCLK_SEL_EXT, 146 CLK_MAC_DIV_SHIFT = 0, 147 CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, 148 149 /* CRU_CLKSEL10_CON */ 150 PERI_PCLK_DIV_SHIFT = 12, 151 PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, 152 PERI_PLL_SEL_SHIFT = 10, 153 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 154 PERI_PLL_CPLL = 0, 155 PERI_PLL_GPLL, 156 PERI_PLL_HDMIPLL, 157 PERI_HCLK_DIV_SHIFT = 8, 158 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 159 PERI_ACLK_DIV_SHIFT = 0, 160 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 161 162 /* CRU_CLKSEL11_CON */ 163 EMMC_PLL_SHIFT = 12, 164 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 165 EMMC_SEL_CPLL = 0, 166 EMMC_SEL_GPLL, 167 EMMC_SEL_24M, 168 SDIO_PLL_SHIFT = 10, 169 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 170 SDIO_SEL_CPLL = 0, 171 SDIO_SEL_GPLL, 172 SDIO_SEL_24M, 173 MMC0_PLL_SHIFT = 8, 174 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 175 MMC0_SEL_CPLL = 0, 176 MMC0_SEL_GPLL, 177 MMC0_SEL_24M, 178 MMC0_DIV_SHIFT = 0, 179 MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, 180 181 /* CRU_CLKSEL12_CON */ 182 EMMC_DIV_SHIFT = 8, 183 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 184 SDIO_DIV_SHIFT = 0, 185 SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, 186 187 /* CRU_CLKSEL26_CON */ 188 DDR_CLK_PLL_SEL_SHIFT = 8, 189 DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, 190 DDR_CLK_SEL_DPLL = 0, 191 DDR_CLK_SEL_GPLL, 192 DDR_CLK_SEL_APLL, 193 DDR_DIV_SEL_SHIFT = 0, 194 DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, 195 196 /* CRU_CLKSEL27_CON */ 197 VOP_DCLK_DIV_SHIFT = 8, 198 VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, 199 VOP_PLL_SEL_SHIFT = 1, 200 VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, 201 202 /* CRU_CLKSEL29_CON */ 203 GMAC_CLK_SRC_SHIFT = 12, 204 GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, 205 206 /* CRU_SOFTRST5_CON */ 207 DDRCTRL_PSRST_SHIFT = 11, 208 DDRCTRL_SRST_SHIFT = 10, 209 DDRPHY_PSRST_SHIFT = 9, 210 DDRPHY_SRST_SHIFT = 8, 211 }; 212 #endif 213