1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _ASM_ARCH_CLOCK_H 8 #define _ASM_ARCH_CLOCK_H 9 10 /* define pll mode */ 11 #define RKCLK_PLL_MODE_SLOW 0 12 #define RKCLK_PLL_MODE_NORMAL 1 13 14 enum { 15 ROCKCHIP_SYSCON_NOC, 16 ROCKCHIP_SYSCON_GRF, 17 ROCKCHIP_SYSCON_SGRF, 18 ROCKCHIP_SYSCON_PMU, 19 ROCKCHIP_SYSCON_PMUGRF, 20 ROCKCHIP_SYSCON_PMUSGRF, 21 ROCKCHIP_SYSCON_CIC, 22 }; 23 24 /* Standard Rockchip clock numbers */ 25 enum rk_clk_id { 26 CLK_OSC, 27 CLK_ARM, 28 CLK_DDR, 29 CLK_CODEC, 30 CLK_GENERAL, 31 CLK_NEW, 32 33 CLK_COUNT, 34 }; 35 36 static inline int rk_pll_id(enum rk_clk_id clk_id) 37 { 38 return clk_id - 1; 39 } 40 41 /** 42 * clk_get_divisor() - Calculate the required clock divisior 43 * 44 * Given an input rate and a required output_rate, calculate the Rockchip 45 * divisor needed to achieve this. 46 * 47 * @input_rate: Input clock rate in Hz 48 * @output_rate: Output clock rate in Hz 49 * @return divisor register value to use 50 */ 51 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 52 { 53 uint clk_div; 54 55 clk_div = input_rate / output_rate; 56 clk_div = (clk_div + 1) & 0xfffe; 57 58 return clk_div; 59 } 60 61 /** 62 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 63 * 64 * @return pointer to registers, or -ve error on error 65 */ 66 void *rockchip_get_cru(void); 67 68 /** 69 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 70 * 71 * @return pointer to registers, or -ve error on error 72 */ 73 void *rockchip_get_pmucru(void); 74 75 struct rk3288_cru; 76 struct rk3288_grf; 77 78 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 79 80 int rockchip_get_clk(struct udevice **devp); 81 82 #endif 83