1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2015 Google, Inc 4 */ 5 6 #ifndef _ASM_ARCH_CLOCK_H 7 #define _ASM_ARCH_CLOCK_H 8 9 /* define pll mode */ 10 #define RKCLK_PLL_MODE_SLOW 0 11 #define RKCLK_PLL_MODE_NORMAL 1 12 13 enum { 14 ROCKCHIP_SYSCON_NOC, 15 ROCKCHIP_SYSCON_GRF, 16 ROCKCHIP_SYSCON_SGRF, 17 ROCKCHIP_SYSCON_PMU, 18 ROCKCHIP_SYSCON_PMUGRF, 19 ROCKCHIP_SYSCON_PMUSGRF, 20 ROCKCHIP_SYSCON_CIC, 21 ROCKCHIP_SYSCON_MSCH, 22 }; 23 24 /* Standard Rockchip clock numbers */ 25 enum rk_clk_id { 26 CLK_OSC, 27 CLK_ARM, 28 CLK_DDR, 29 CLK_CODEC, 30 CLK_GENERAL, 31 CLK_NEW, 32 33 CLK_COUNT, 34 }; 35 36 static inline int rk_pll_id(enum rk_clk_id clk_id) 37 { 38 return clk_id - 1; 39 } 40 41 struct sysreset_reg { 42 unsigned int glb_srst_fst_value; 43 unsigned int glb_srst_snd_value; 44 }; 45 46 /** 47 * clk_get_divisor() - Calculate the required clock divisior 48 * 49 * Given an input rate and a required output_rate, calculate the Rockchip 50 * divisor needed to achieve this. 51 * 52 * @input_rate: Input clock rate in Hz 53 * @output_rate: Output clock rate in Hz 54 * @return divisor register value to use 55 */ 56 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) 57 { 58 uint clk_div; 59 60 clk_div = input_rate / output_rate; 61 clk_div = (clk_div + 1) & 0xfffe; 62 63 return clk_div; 64 } 65 66 /** 67 * rockchip_get_cru() - get a pointer to the clock/reset unit registers 68 * 69 * @return pointer to registers, or -ve error on error 70 */ 71 void *rockchip_get_cru(void); 72 73 /** 74 * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers 75 * 76 * @return pointer to registers, or -ve error on error 77 */ 78 void *rockchip_get_pmucru(void); 79 80 struct rk3288_cru; 81 struct rk3288_grf; 82 83 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); 84 85 int rockchip_get_clk(struct udevice **devp); 86 87 /* 88 * rockchip_reset_bind() - Bind soft reset device as child of clock device 89 * 90 * @pdev: clock udevice 91 * @reg_offset: the first offset in cru for softreset registers 92 * @reg_number: the reg numbers of softreset registers 93 * @return 0 success, or error value 94 */ 95 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); 96 97 #endif 98