1 /* 2 * PXA25x UDC definitions 3 * 4 * Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #ifndef __REGS_USB_H__ 22 #define __REGS_USB_H__ 23 24 struct pxa25x_udc_regs { 25 /* UDC Control Register */ 26 uint32_t udccr; /* 0x000 */ 27 uint32_t reserved1; 28 29 /* UDC Control Function Register */ 30 uint32_t udccfr; /* 0x008 */ 31 uint32_t reserved2; 32 33 /* UDC Endpoint Control/Status Registers */ 34 uint32_t udccs[16]; /* 0x010 - 0x04c */ 35 36 /* UDC Interrupt Control/Status Registers */ 37 uint32_t uicr0; /* 0x050 */ 38 uint32_t uicr1; /* 0x054 */ 39 uint32_t usir0; /* 0x058 */ 40 uint32_t usir1; /* 0x05c */ 41 42 /* UDC Frame Number/Byte Count Registers */ 43 uint32_t ufnrh; /* 0x060 */ 44 uint32_t ufnrl; /* 0x064 */ 45 uint32_t ubcr2; /* 0x068 */ 46 uint32_t ubcr4; /* 0x06c */ 47 uint32_t ubcr7; /* 0x070 */ 48 uint32_t ubcr9; /* 0x074 */ 49 uint32_t ubcr12; /* 0x078 */ 50 uint32_t ubcr14; /* 0x07c */ 51 52 /* UDC Endpoint Data Registers */ 53 uint32_t uddr0; /* 0x080 */ 54 uint32_t reserved3[7]; 55 uint32_t uddr5; /* 0x0a0 */ 56 uint32_t reserved4[7]; 57 uint32_t uddr10; /* 0x0c0 */ 58 uint32_t reserved5[7]; 59 uint32_t uddr15; /* 0x0e0 */ 60 uint32_t reserved6[7]; 61 uint32_t uddr1; /* 0x100 */ 62 uint32_t reserved7[31]; 63 uint32_t uddr2; /* 0x180 */ 64 uint32_t reserved8[31]; 65 uint32_t uddr3; /* 0x200 */ 66 uint32_t reserved9[127]; 67 uint32_t uddr4; /* 0x400 */ 68 uint32_t reserved10[127]; 69 uint32_t uddr6; /* 0x600 */ 70 uint32_t reserved11[31]; 71 uint32_t uddr7; /* 0x680 */ 72 uint32_t reserved12[31]; 73 uint32_t uddr8; /* 0x700 */ 74 uint32_t reserved13[127]; 75 uint32_t uddr9; /* 0x900 */ 76 uint32_t reserved14[127]; 77 uint32_t uddr11; /* 0xb00 */ 78 uint32_t reserved15[31]; 79 uint32_t uddr12; /* 0xb80 */ 80 uint32_t reserved16[31]; 81 uint32_t uddr13; /* 0xc00 */ 82 uint32_t reserved17[127]; 83 uint32_t uddr14; /* 0xe00 */ 84 85 }; 86 87 #define PXA25X_UDC_BASE 0x40600000 88 89 #define UDCCR_UDE (1 << 0) 90 #define UDCCR_UDA (1 << 1) 91 #define UDCCR_RSM (1 << 2) 92 #define UDCCR_RESIR (1 << 3) 93 #define UDCCR_SUSIR (1 << 4) 94 #define UDCCR_SRM (1 << 5) 95 #define UDCCR_RSTIR (1 << 6) 96 #define UDCCR_REM (1 << 7) 97 98 /* Bulk IN endpoint 1/6/11 */ 99 #define UDCCS_BI_TSP (1 << 7) 100 #define UDCCS_BI_FST (1 << 5) 101 #define UDCCS_BI_SST (1 << 4) 102 #define UDCCS_BI_TUR (1 << 3) 103 #define UDCCS_BI_FTF (1 << 2) 104 #define UDCCS_BI_TPC (1 << 1) 105 #define UDCCS_BI_TFS (1 << 0) 106 107 /* Bulk OUT endpoint 2/7/12 */ 108 #define UDCCS_BO_RSP (1 << 7) 109 #define UDCCS_BO_RNE (1 << 6) 110 #define UDCCS_BO_FST (1 << 5) 111 #define UDCCS_BO_SST (1 << 4) 112 #define UDCCS_BO_DME (1 << 3) 113 #define UDCCS_BO_RPC (1 << 1) 114 #define UDCCS_BO_RFS (1 << 0) 115 116 /* Isochronous OUT endpoint 4/9/14 */ 117 #define UDCCS_IO_RSP (1 << 7) 118 #define UDCCS_IO_RNE (1 << 6) 119 #define UDCCS_IO_DME (1 << 3) 120 #define UDCCS_IO_ROF (1 << 2) 121 #define UDCCS_IO_RPC (1 << 1) 122 #define UDCCS_IO_RFS (1 << 0) 123 124 /* Control endpoint 0 */ 125 #define UDCCS0_OPR (1 << 0) 126 #define UDCCS0_IPR (1 << 1) 127 #define UDCCS0_FTF (1 << 2) 128 #define UDCCS0_DRWF (1 << 3) 129 #define UDCCS0_SST (1 << 4) 130 #define UDCCS0_FST (1 << 5) 131 #define UDCCS0_RNE (1 << 6) 132 #define UDCCS0_SA (1 << 7) 133 134 #define UICR0_IM0 (1 << 0) 135 136 #define USIR0_IR0 (1 << 0) 137 #define USIR0_IR1 (1 << 1) 138 #define USIR0_IR2 (1 << 2) 139 #define USIR0_IR3 (1 << 3) 140 #define USIR0_IR4 (1 << 4) 141 #define USIR0_IR5 (1 << 5) 142 #define USIR0_IR6 (1 << 6) 143 #define USIR0_IR7 (1 << 7) 144 145 #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ 146 #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ 147 /* 148 * Intel(R) PXA255 Processor Specification, September 2003 (page 31) 149 * define new "must be one" bits in UDCCFR (see Table 12-13.) 150 */ 151 #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM)) 152 153 #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ 154 #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ 155 #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ 156 #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ 157 #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ 158 159 #endif /* __REGS_USB_H__ */ 160