1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 207133f2eSMarek Vasut /* 307133f2eSMarek Vasut * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 407133f2eSMarek Vasut */ 507133f2eSMarek Vasut 607133f2eSMarek Vasut #ifndef __REGS_MMC_H__ 707133f2eSMarek Vasut #define __REGS_MMC_H__ 807133f2eSMarek Vasut 907133f2eSMarek Vasut #define MMC0_BASE 0x41100000 1007133f2eSMarek Vasut #define MMC1_BASE 0x42000000 1107133f2eSMarek Vasut 1207133f2eSMarek Vasut int pxa_mmc_register(int card_index); 1307133f2eSMarek Vasut 1407133f2eSMarek Vasut struct pxa_mmc_regs { 1507133f2eSMarek Vasut uint32_t strpcl; 1607133f2eSMarek Vasut uint32_t stat; 1707133f2eSMarek Vasut uint32_t clkrt; 1807133f2eSMarek Vasut uint32_t spi; 1907133f2eSMarek Vasut uint32_t cmdat; 2007133f2eSMarek Vasut uint32_t resto; 2107133f2eSMarek Vasut uint32_t rdto; 2207133f2eSMarek Vasut uint32_t blklen; 2307133f2eSMarek Vasut uint32_t nob; 2407133f2eSMarek Vasut uint32_t prtbuf; 2507133f2eSMarek Vasut uint32_t i_mask; 2607133f2eSMarek Vasut uint32_t i_reg; 2707133f2eSMarek Vasut uint32_t cmd; 2807133f2eSMarek Vasut uint32_t argh; 2907133f2eSMarek Vasut uint32_t argl; 3007133f2eSMarek Vasut uint32_t res; 3107133f2eSMarek Vasut uint32_t rxfifo; 3207133f2eSMarek Vasut uint32_t txfifo; 3307133f2eSMarek Vasut }; 3407133f2eSMarek Vasut 3507133f2eSMarek Vasut /* MMC_STRPCL */ 3607133f2eSMarek Vasut #define MMC_STRPCL_STOP_CLK (1 << 0) 3707133f2eSMarek Vasut #define MMC_STRPCL_START_CLK (1 << 1) 3807133f2eSMarek Vasut 3907133f2eSMarek Vasut /* MMC_STAT */ 4007133f2eSMarek Vasut #define MMC_STAT_END_CMD_RES (1 << 13) 4107133f2eSMarek Vasut #define MMC_STAT_PRG_DONE (1 << 12) 4207133f2eSMarek Vasut #define MMC_STAT_DATA_TRAN_DONE (1 << 11) 4307133f2eSMarek Vasut #define MMC_STAT_CLK_EN (1 << 8) 4407133f2eSMarek Vasut #define MMC_STAT_RECV_FIFO_FULL (1 << 7) 4507133f2eSMarek Vasut #define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) 4607133f2eSMarek Vasut #define MMC_STAT_RES_CRC_ERROR (1 << 5) 4707133f2eSMarek Vasut #define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) 4807133f2eSMarek Vasut #define MMC_STAT_CRC_READ_ERROR (1 << 3) 4907133f2eSMarek Vasut #define MMC_STAT_CRC_WRITE_ERROR (1 << 2) 5007133f2eSMarek Vasut #define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) 5107133f2eSMarek Vasut #define MMC_STAT_READ_TIME_OUT (1 << 0) 5207133f2eSMarek Vasut 5307133f2eSMarek Vasut /* MMC_CLKRT */ 5407133f2eSMarek Vasut #define MMC_CLKRT_20MHZ 0 5507133f2eSMarek Vasut #define MMC_CLKRT_10MHZ 1 5607133f2eSMarek Vasut #define MMC_CLKRT_5MHZ 2 5707133f2eSMarek Vasut #define MMC_CLKRT_2_5MHZ 3 5807133f2eSMarek Vasut #define MMC_CLKRT_1_25MHZ 4 5907133f2eSMarek Vasut #define MMC_CLKRT_0_625MHZ 5 6007133f2eSMarek Vasut #define MMC_CLKRT_0_3125MHZ 6 6107133f2eSMarek Vasut 6207133f2eSMarek Vasut /* MMC_SPI */ 6307133f2eSMarek Vasut #define MMC_SPI_EN (1 << 0) 6407133f2eSMarek Vasut #define MMC_SPI_CS_EN (1 << 2) 6507133f2eSMarek Vasut #define MMC_SPI_CS_ADDRESS (1 << 3) 6607133f2eSMarek Vasut #define MMC_SPI_CRC_ON (1 << 1) 6707133f2eSMarek Vasut 6807133f2eSMarek Vasut /* MMC_CMDAT */ 6907133f2eSMarek Vasut #define MMC_CMDAT_SD_4DAT (1 << 8) 7007133f2eSMarek Vasut #define MMC_CMDAT_MMC_DMA_EN (1 << 7) 7107133f2eSMarek Vasut #define MMC_CMDAT_INIT (1 << 6) 7207133f2eSMarek Vasut #define MMC_CMDAT_BUSY (1 << 5) 7307133f2eSMarek Vasut #define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) 7407133f2eSMarek Vasut #define MMC_CMDAT_STREAM (1 << 4) 7507133f2eSMarek Vasut #define MMC_CMDAT_WRITE (1 << 3) 7607133f2eSMarek Vasut #define MMC_CMDAT_DATA_EN (1 << 2) 7707133f2eSMarek Vasut #define MMC_CMDAT_R0 0 7807133f2eSMarek Vasut #define MMC_CMDAT_R1 1 7907133f2eSMarek Vasut #define MMC_CMDAT_R2 2 8007133f2eSMarek Vasut #define MMC_CMDAT_R3 3 8107133f2eSMarek Vasut 8207133f2eSMarek Vasut /* MMC_RESTO */ 8307133f2eSMarek Vasut #define MMC_RES_TO_MAX_MASK 0x7f 8407133f2eSMarek Vasut 8507133f2eSMarek Vasut /* MMC_RDTO */ 8607133f2eSMarek Vasut #define MMC_READ_TO_MAX_MASK 0xffff 8707133f2eSMarek Vasut 8807133f2eSMarek Vasut /* MMC_BLKLEN */ 8907133f2eSMarek Vasut #define MMC_BLK_LEN_MAX_MASK 0x3ff 9007133f2eSMarek Vasut 9107133f2eSMarek Vasut /* MMC_PRTBUF */ 9207133f2eSMarek Vasut #define MMC_PRTBUF_BUF_PART_FULL (1 << 0) 9307133f2eSMarek Vasut 9407133f2eSMarek Vasut /* MMC_I_MASK */ 9507133f2eSMarek Vasut #define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) 9607133f2eSMarek Vasut #define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) 9707133f2eSMarek Vasut #define MMC_I_MASK_CLK_IS_OFF (1 << 4) 9807133f2eSMarek Vasut #define MMC_I_MASK_STOP_CMD (1 << 3) 9907133f2eSMarek Vasut #define MMC_I_MASK_END_CMD_RES (1 << 2) 10007133f2eSMarek Vasut #define MMC_I_MASK_PRG_DONE (1 << 1) 10107133f2eSMarek Vasut #define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) 10207133f2eSMarek Vasut #define MMC_I_MASK_ALL 0x7f 10307133f2eSMarek Vasut 10407133f2eSMarek Vasut 10507133f2eSMarek Vasut /* MMC_I_REG */ 10607133f2eSMarek Vasut #define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) 10707133f2eSMarek Vasut #define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) 10807133f2eSMarek Vasut #define MMC_I_REG_CLK_IS_OFF (1 << 4) 10907133f2eSMarek Vasut #define MMC_I_REG_STOP_CMD (1 << 3) 11007133f2eSMarek Vasut #define MMC_I_REG_END_CMD_RES (1 << 2) 11107133f2eSMarek Vasut #define MMC_I_REG_PRG_DONE (1 << 1) 11207133f2eSMarek Vasut #define MMC_I_REG_DATA_TRAN_DONE (1 << 0) 11307133f2eSMarek Vasut 11407133f2eSMarek Vasut /* MMC_CMD */ 11507133f2eSMarek Vasut #define MMC_CMD_INDEX_MAX 0x6f 11607133f2eSMarek Vasut 11707133f2eSMarek Vasut #define MMC_R1_IDLE_STATE 0x01 11807133f2eSMarek Vasut #define MMC_R1_ERASE_STATE 0x02 11907133f2eSMarek Vasut #define MMC_R1_ILLEGAL_CMD 0x04 12007133f2eSMarek Vasut #define MMC_R1_COM_CRC_ERR 0x08 12107133f2eSMarek Vasut #define MMC_R1_ERASE_SEQ_ERR 0x01 12207133f2eSMarek Vasut #define MMC_R1_ADDR_ERR 0x02 12307133f2eSMarek Vasut #define MMC_R1_PARAM_ERR 0x04 12407133f2eSMarek Vasut 12507133f2eSMarek Vasut #define MMC_R1B_WP_ERASE_SKIP 0x0002 12607133f2eSMarek Vasut #define MMC_R1B_ERR 0x0004 12707133f2eSMarek Vasut #define MMC_R1B_CC_ERR 0x0008 12807133f2eSMarek Vasut #define MMC_R1B_CARD_ECC_ERR 0x0010 12907133f2eSMarek Vasut #define MMC_R1B_WP_VIOLATION 0x0020 13007133f2eSMarek Vasut #define MMC_R1B_ERASE_PARAM 0x0040 13107133f2eSMarek Vasut #define MMC_R1B_OOR 0x0080 13207133f2eSMarek Vasut #define MMC_R1B_IDLE_STATE 0x0100 13307133f2eSMarek Vasut #define MMC_R1B_ERASE_RESET 0x0200 13407133f2eSMarek Vasut #define MMC_R1B_ILLEGAL_CMD 0x0400 13507133f2eSMarek Vasut #define MMC_R1B_COM_CRC_ERR 0x0800 13607133f2eSMarek Vasut #define MMC_R1B_ERASE_SEQ_ERR 0x1000 13707133f2eSMarek Vasut #define MMC_R1B_ADDR_ERR 0x2000 13807133f2eSMarek Vasut #define MMC_R1B_PARAM_ERR 0x4000 13907133f2eSMarek Vasut 14007133f2eSMarek Vasut #endif /* __REGS_MMC_H__ */ 141