1508a58faSSricharan /* 2508a58faSSricharan * (C) Copyright 2010 3508a58faSSricharan * Texas Instruments, <www.ti.com> 4508a58faSSricharan * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6508a58faSSricharan */ 7508a58faSSricharan 8508a58faSSricharan #ifndef _SYS_PROTO_H_ 9508a58faSSricharan #define _SYS_PROTO_H_ 10508a58faSSricharan 11508a58faSSricharan #include <asm/arch/omap.h> 12508a58faSSricharan #include <asm/io.h> 13af1d002fSLokesh Vutla #include <asm/arch/clock.h> 14508a58faSSricharan #include <asm/omap_common.h> 156aff0509Spekon gupta #include <linux/mtd/omap_gpmc.h> 16af1d002fSLokesh Vutla #include <asm/arch/clock.h> 17939911a6STom Rini #include <asm/ti-common/sys_proto.h> 18508a58faSSricharan 194a0eb757SSRICHARAN R DECLARE_GLOBAL_DATA_PTR; 204a0eb757SSRICHARAN R 2171bed185SLokesh Vutla /* 2271bed185SLokesh Vutla * Structure for Iodelay configuration registers. 2371bed185SLokesh Vutla * Theoretical max for g_delay is 21560 ps. 2471bed185SLokesh Vutla * Theoretical max for a_delay is 1/3rd of g_delay max. 2571bed185SLokesh Vutla * So using u16 for both a/g_delay. 2671bed185SLokesh Vutla */ 2771bed185SLokesh Vutla struct iodelay_cfg_entry { 2871bed185SLokesh Vutla u16 offset; 2971bed185SLokesh Vutla u16 a_delay; 3071bed185SLokesh Vutla u16 g_delay; 3171bed185SLokesh Vutla }; 3271bed185SLokesh Vutla 33687054a7SLokesh Vutla struct pad_conf_entry { 34687054a7SLokesh Vutla u32 offset; 35687054a7SLokesh Vutla u32 val; 36687054a7SLokesh Vutla }; 37687054a7SLokesh Vutla 38508a58faSSricharan struct omap_sysinfo { 39508a58faSSricharan char *board_string; 40508a58faSSricharan }; 41508a58faSSricharan extern const struct omap_sysinfo sysinfo; 42508a58faSSricharan 43508a58faSSricharan void gpmc_init(void); 44508a58faSSricharan void watchdog_init(void); 45508a58faSSricharan u32 get_device_type(void); 46508a58faSSricharan void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); 471f68451cSLokesh Vutla void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); 48508a58faSSricharan void set_muxconf_regs_essential(void); 49508a58faSSricharan u32 wait_on_value(u32, u32, void *, u32); 50508a58faSSricharan void sdelay(unsigned long); 51*93e6253dSKipisz, Steven void setup_early_clocks(void); 52508a58faSSricharan void prcm_init(void); 5301b753ffSSRICHARAN R void bypass_dpll(u32 const base); 54508a58faSSricharan void freq_update_core(void); 55508a58faSSricharan u32 get_sys_clk_freq(void); 56508a58faSSricharan u32 omap5_ddr_clk(void); 57508a58faSSricharan void cancel_out(u32 *num, u32 *den, u32 den_limit); 58508a58faSSricharan void sdram_init(void); 59508a58faSSricharan u32 omap_sdram_size(void); 60508a58faSSricharan u32 cortex_rev(void); 614596dcc1STom Rini void save_omap_boot_params(void); 62508a58faSSricharan void init_omap_revision(void); 63508a58faSSricharan void do_io_settings(void); 644ca94d81SLokesh Vutla void sri2c_init(void); 6563fc0c77SLokesh Vutla void gpi2c_init(void); 66a78274b2SNishanth Menon int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); 6770239507SLokesh Vutla u32 warm_reset(void); 6838f25b12SLokesh Vutla void force_emif_self_refresh(void); 69ef1697e9SLokesh Vutla void get_ioregs(const struct ctrl_ioregs **regs); 70d4d986eeSLokesh Vutla void srcomp_enable(void); 710b1b60c7SLokesh Vutla void setup_warmreset_time(void); 72508a58faSSricharan 730b1b60c7SLokesh Vutla static inline u32 div_round_up(u32 num, u32 den) 740b1b60c7SLokesh Vutla { 750b1b60c7SLokesh Vutla return (num + den - 1)/den; 760b1b60c7SLokesh Vutla } 770b1b60c7SLokesh Vutla 780b1b60c7SLokesh Vutla static inline u32 usec_to_32k(u32 usec) 790b1b60c7SLokesh Vutla { 800b1b60c7SLokesh Vutla return div_round_up(32768 * usec, 1000000); 810b1b60c7SLokesh Vutla } 825f603761SPraveen Rao 835f603761SPraveen Rao #define OMAP5_SERVICE_L2ACTLR_SET 0x104 841bbb556aSNishanth Menon #define OMAP5_SERVICE_ACR_SET 0x107 855f603761SPraveen Rao 86508a58faSSricharan #endif 87