1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _OMAP5_H_ 13 #define _OMAP5_H_ 14 15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16 #include <asm/types.h> 17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18 19 /* 20 * L4 Peripherals - L4 Wakeup and L4 Core now 21 */ 22 #define OMAP54XX_L4_CORE_BASE 0x4A000000 23 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 24 #define OMAP54XX_L4_PER_BASE 0x48000000 25 26 /* CONTROL ID CODE */ 27 #define CONTROL_CORE_ID_CODE 0x4A002204 28 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 29 30 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 31 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE 32 #else 33 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE 34 #endif 35 36 #ifdef CONFIG_DRA7XX 37 #define DRA7_USB_OTG_SS1_BASE 0x48890000 38 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 39 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 40 #define DRA7_USB3_PHY1_POWER 0x4A002370 41 #define DRA7_USB2_PHY1_POWER 0x4A002300 42 43 #define DRA7_USB_OTG_SS2_BASE 0x488D0000 44 #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 45 #define DRA7_USB2_PHY2_POWER 0x4A002E74 46 #endif 47 48 /* To be verified */ 49 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 50 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 51 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 52 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 53 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 54 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 55 #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F 56 57 /* UART */ 58 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 59 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 60 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 61 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) 62 63 /* General Purpose Timers */ 64 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 65 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 66 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 67 68 /* Watchdog Timer2 - MPU watchdog */ 69 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 70 71 /* QSPI */ 72 #define QSPI_BASE 0x4B300000 73 74 /* SATA */ 75 #define DWC_AHSATA_BASE 0x4A140000 76 77 /* 78 * Hardware Register Details 79 */ 80 81 /* Watchdog Timer */ 82 #define WD_UNLOCK1 0xAAAA 83 #define WD_UNLOCK2 0x5555 84 85 /* GP Timer */ 86 #define TCLR_ST (0x1 << 0) 87 #define TCLR_AR (0x1 << 1) 88 #define TCLR_PRE (0x1 << 5) 89 90 /* Control Module */ 91 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 92 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 93 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 94 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 95 96 /* LPDDR2 IO regs */ 97 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 98 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 99 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 100 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 101 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 102 103 /* CONTROL_EFUSE_2 */ 104 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 105 106 #define SDCARD_BIAS_PWRDNZ (1 << 27) 107 #define SDCARD_PWRDNZ (1 << 26) 108 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 109 #define SDCARD_PBIASLITE_VMODE (1 << 21) 110 111 #ifndef __ASSEMBLY__ 112 113 struct s32ktimer { 114 unsigned char res[0x10]; 115 unsigned int s32k_cr; /* 0x10 */ 116 }; 117 118 #define DEVICE_TYPE_SHIFT 0x6 119 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 120 #define DEVICE_GP 0x3 121 122 /* Output impedance control */ 123 #define ds_120_ohm 0x0 124 #define ds_60_ohm 0x1 125 #define ds_45_ohm 0x2 126 #define ds_30_ohm 0x3 127 #define ds_mask 0x3 128 129 /* Slew rate control */ 130 #define sc_slow 0x0 131 #define sc_medium 0x1 132 #define sc_fast 0x2 133 #define sc_na 0x3 134 #define sc_mask 0x3 135 136 /* Target capacitance control */ 137 #define lb_5_12_pf 0x0 138 #define lb_12_25_pf 0x1 139 #define lb_25_50_pf 0x2 140 #define lb_50_80_pf 0x3 141 #define lb_mask 0x3 142 143 #define usb_i_mask 0x7 144 145 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 146 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 147 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 148 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 149 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 150 151 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 152 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 153 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 154 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 155 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 156 157 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 158 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 159 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 160 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC 161 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 162 163 #define EFUSE_1 0x45145100 164 #define EFUSE_2 0x45145100 165 #define EFUSE_3 0x45145100 166 #define EFUSE_4 0x45145100 167 #endif /* __ASSEMBLY__ */ 168 169 /* 170 * In all cases, the TRM defines the RAM Memory Map for the processor 171 * and indicates the area for the downloaded image. We use all of that 172 * space for download and once up and running may use other parts of the 173 * map for our needs. We set a scratch space that is at the end of the 174 * OMAP5 download area, but within the DRA7xx download area (as it is 175 * much larger) and do not, at this time, make use of the additional 176 * space. 177 */ 178 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 179 #define NON_SECURE_SRAM_START 0x40300000 180 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 181 #else 182 #define NON_SECURE_SRAM_START 0x40300000 183 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 184 #endif 185 #define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 186 187 /* base address for indirect vectors (internal boot mode) */ 188 #define SRAM_ROM_VECT_BASE 0x4031F000 189 190 /* CONTROL_SRCOMP_XXX_SIDE */ 191 #define OVERRIDE_XS_SHIFT 30 192 #define OVERRIDE_XS_MASK (1 << 30) 193 #define SRCODE_READ_XS_SHIFT 12 194 #define SRCODE_READ_XS_MASK (0xff << 12) 195 #define PWRDWN_XS_SHIFT 11 196 #define PWRDWN_XS_MASK (1 << 11) 197 #define DIVIDE_FACTOR_XS_SHIFT 4 198 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 199 #define MULTIPLY_FACTOR_XS_SHIFT 1 200 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 201 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 202 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 203 204 /* ABB settings */ 205 #define OMAP_ABB_SETTLING_TIME 50 206 #define OMAP_ABB_CLOCK_CYCLES 16 207 208 /* ABB tranxdone mask */ 209 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 210 211 /* ABB efuse masks */ 212 #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) 213 #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) 214 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) 215 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) 216 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) 217 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) 218 219 /* IO Delay module defines */ 220 #define CFG_IO_DELAY_BASE 0x4844A000 221 #define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) 222 223 /* CPSW IO Delay registers*/ 224 #define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) 225 #define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) 226 #define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) 227 #define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) 228 #define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) 229 #define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) 230 #define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) 231 #define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) 232 #define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) 233 #define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) 234 235 #define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA 236 #define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB 237 #define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 238 #define CFG_IO_DELAY_LOCK_MASK 0x400 239 240 #ifndef __ASSEMBLY__ 241 struct srcomp_params { 242 s8 divide_factor; 243 s8 multiply_factor; 244 }; 245 246 struct ctrl_ioregs { 247 u32 ctrl_ddrch; 248 u32 ctrl_lpddr2ch; 249 u32 ctrl_ddr3ch; 250 u32 ctrl_ddrio_0; 251 u32 ctrl_ddrio_1; 252 u32 ctrl_ddrio_2; 253 u32 ctrl_emif_sdram_config_ext; 254 u32 ctrl_emif_sdram_config_ext_final; 255 u32 ctrl_ddr_ctrl_ext_0; 256 }; 257 258 struct io_delay { 259 u32 addr; 260 u32 dly; 261 }; 262 #endif /* __ASSEMBLY__ */ 263 #endif 264