1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _OMAP5_H_ 13 #define _OMAP5_H_ 14 15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16 #include <asm/types.h> 17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18 19 /* 20 * L4 Peripherals - L4 Wakeup and L4 Core now 21 */ 22 #define OMAP54XX_L4_CORE_BASE 0x4A000000 23 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 24 #define OMAP54XX_L4_PER_BASE 0x48000000 25 26 /* CONTROL ID CODE */ 27 #define CONTROL_CORE_ID_CODE 0x4A002204 28 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 29 30 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 31 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE 32 #else 33 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE 34 #endif 35 36 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 37 #define DRA7_USB_OTG_SS1_BASE 0x48890000 38 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 39 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 40 #define DRA7_USB3_PHY1_POWER 0x4A002370 41 #define DRA7_USB2_PHY1_POWER 0x4A002300 42 43 #define DRA7_USB_OTG_SS2_BASE 0x488D0000 44 #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 45 #define DRA7_USB2_PHY2_POWER 0x4A002E74 46 #else 47 #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 48 #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 49 #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 50 #define OMAP5XX_USB3_PHY_POWER 0x4A002370 51 #define OMAP5XX_USB2_PHY_POWER 0x4A002300 52 #endif 53 54 /* To be verified */ 55 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 56 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 57 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 58 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 59 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 60 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 61 #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F 62 #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F 63 #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F 64 65 /* UART */ 66 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 67 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 68 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 69 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) 70 71 /* General Purpose Timers */ 72 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 73 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 74 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 75 76 /* Watchdog Timer2 - MPU watchdog */ 77 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 78 79 /* QSPI */ 80 #define QSPI_BASE 0x4B300000 81 82 /* SATA */ 83 #define DWC_AHSATA_BASE 0x4A140000 84 85 /* 86 * Hardware Register Details 87 */ 88 89 /* Watchdog Timer */ 90 #define WD_UNLOCK1 0xAAAA 91 #define WD_UNLOCK2 0x5555 92 93 /* GP Timer */ 94 #define TCLR_ST (0x1 << 0) 95 #define TCLR_AR (0x1 << 1) 96 #define TCLR_PRE (0x1 << 5) 97 98 /* Control Module */ 99 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 100 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 101 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 102 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 103 104 /* LPDDR2 IO regs */ 105 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 106 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 107 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 108 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 109 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 110 111 /* CONTROL_EFUSE_2 */ 112 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 113 114 #define SDCARD_BIAS_PWRDNZ (1 << 27) 115 #define SDCARD_PWRDNZ (1 << 26) 116 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 117 #define SDCARD_PBIASLITE_VMODE (1 << 21) 118 119 #ifndef __ASSEMBLY__ 120 121 struct s32ktimer { 122 unsigned char res[0x10]; 123 unsigned int s32k_cr; /* 0x10 */ 124 }; 125 126 #define DEVICE_TYPE_SHIFT 0x6 127 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 128 #define DEVICE_GP 0x3 129 130 /* Output impedance control */ 131 #define ds_120_ohm 0x0 132 #define ds_60_ohm 0x1 133 #define ds_45_ohm 0x2 134 #define ds_30_ohm 0x3 135 #define ds_mask 0x3 136 137 /* Slew rate control */ 138 #define sc_slow 0x0 139 #define sc_medium 0x1 140 #define sc_fast 0x2 141 #define sc_na 0x3 142 #define sc_mask 0x3 143 144 /* Target capacitance control */ 145 #define lb_5_12_pf 0x0 146 #define lb_12_25_pf 0x1 147 #define lb_25_50_pf 0x2 148 #define lb_50_80_pf 0x3 149 #define lb_mask 0x3 150 151 #define usb_i_mask 0x7 152 153 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 154 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 155 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 156 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 157 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 158 159 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 160 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 161 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 162 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 163 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 164 165 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 166 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 167 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 168 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC 169 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 170 171 #define EFUSE_1 0x45145100 172 #define EFUSE_2 0x45145100 173 #define EFUSE_3 0x45145100 174 #define EFUSE_4 0x45145100 175 #endif /* __ASSEMBLY__ */ 176 177 /* 178 * In all cases, the TRM defines the RAM Memory Map for the processor 179 * and indicates the area for the downloaded image. We use all of that 180 * space for download and once up and running may use other parts of the 181 * map for our needs. We set a scratch space that is at the end of the 182 * OMAP5 download area, but within the DRA7xx download area (as it is 183 * much larger) and do not, at this time, make use of the additional 184 * space. 185 */ 186 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 187 #define NON_SECURE_SRAM_START 0x40300000 188 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 189 #else 190 #define NON_SECURE_SRAM_START 0x40300000 191 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 192 #endif 193 #define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 194 195 /* base address for indirect vectors (internal boot mode) */ 196 #define SRAM_ROM_VECT_BASE 0x4031F000 197 198 /* CONTROL_SRCOMP_XXX_SIDE */ 199 #define OVERRIDE_XS_SHIFT 30 200 #define OVERRIDE_XS_MASK (1 << 30) 201 #define SRCODE_READ_XS_SHIFT 12 202 #define SRCODE_READ_XS_MASK (0xff << 12) 203 #define PWRDWN_XS_SHIFT 11 204 #define PWRDWN_XS_MASK (1 << 11) 205 #define DIVIDE_FACTOR_XS_SHIFT 4 206 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 207 #define MULTIPLY_FACTOR_XS_SHIFT 1 208 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 209 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 210 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 211 212 /* ABB settings */ 213 #define OMAP_ABB_SETTLING_TIME 50 214 #define OMAP_ABB_CLOCK_CYCLES 16 215 216 /* ABB tranxdone mask */ 217 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 218 #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) 219 #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) 220 #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) 221 #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) 222 223 /* ABB efuse masks */ 224 #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) 225 #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) 226 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) 227 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) 228 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) 229 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) 230 231 #ifndef __ASSEMBLY__ 232 struct srcomp_params { 233 s8 divide_factor; 234 s8 multiply_factor; 235 }; 236 237 struct ctrl_ioregs { 238 u32 ctrl_ddrch; 239 u32 ctrl_lpddr2ch; 240 u32 ctrl_ddr3ch; 241 u32 ctrl_ddrio_0; 242 u32 ctrl_ddrio_1; 243 u32 ctrl_ddrio_2; 244 u32 ctrl_emif_sdram_config_ext; 245 u32 ctrl_emif_sdram_config_ext_final; 246 u32 ctrl_ddr_ctrl_ext_0; 247 }; 248 249 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); 250 251 #endif /* __ASSEMBLY__ */ 252 253 /* Boot parameters */ 254 #ifndef __ASSEMBLY__ 255 struct omap_boot_parameters { 256 unsigned int boot_message; 257 unsigned int boot_device_descriptor; 258 unsigned char boot_device; 259 unsigned char reset_reason; 260 unsigned char ch_flags; 261 }; 262 #endif 263 264 #endif 265