1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _OMAP5_H_ 13 #define _OMAP5_H_ 14 15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16 #include <asm/types.h> 17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18 19 #include <linux/sizes.h> 20 21 /* 22 * L4 Peripherals - L4 Wakeup and L4 Core now 23 */ 24 #define OMAP54XX_L4_CORE_BASE 0x4A000000 25 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 26 #define OMAP54XX_L4_PER_BASE 0x48000000 27 28 /* CONTROL ID CODE */ 29 #define CONTROL_CORE_ID_CODE 0x4A002204 30 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 31 32 #if defined(CONFIG_DRA7XX) 33 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE 34 #else 35 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE 36 #endif 37 38 #if defined(CONFIG_DRA7XX) 39 #define DRA7_USB_OTG_SS1_BASE 0x48890000 40 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 41 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 42 #define DRA7_USB3_PHY1_POWER 0x4A002370 43 #define DRA7_USB2_PHY1_POWER 0x4A002300 44 45 #define DRA7_USB_OTG_SS2_BASE 0x488D0000 46 #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 47 #define DRA7_USB2_PHY2_POWER 0x4A002E74 48 #else 49 #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 50 #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 51 #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 52 #define OMAP5XX_USB3_PHY_POWER 0x4A002370 53 #define OMAP5XX_USB2_PHY_POWER 0x4A002300 54 #endif 55 56 /* To be verified */ 57 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 58 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 59 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 60 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 61 #define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F 62 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 63 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 64 #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F 65 #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F 66 #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F 67 #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F 68 69 /* UART */ 70 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 71 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 72 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 73 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) 74 75 /* General Purpose Timers */ 76 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 77 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 78 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 79 80 /* Watchdog Timer2 - MPU watchdog */ 81 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 82 83 /* QSPI */ 84 #define QSPI_BASE 0x4B300000 85 86 /* SATA */ 87 #define DWC_AHSATA_BASE 0x4A140000 88 89 /* 90 * Hardware Register Details 91 */ 92 93 /* Watchdog Timer */ 94 #define WD_UNLOCK1 0xAAAA 95 #define WD_UNLOCK2 0x5555 96 97 /* GP Timer */ 98 #define TCLR_ST (0x1 << 0) 99 #define TCLR_AR (0x1 << 1) 100 #define TCLR_PRE (0x1 << 5) 101 102 /* Control Module */ 103 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 104 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 105 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 106 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 107 108 /* LPDDR2 IO regs */ 109 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 110 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 111 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 112 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 113 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 114 115 /* CONTROL_EFUSE_2 */ 116 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 117 118 #define SDCARD_BIAS_PWRDNZ (1 << 27) 119 #define SDCARD_PWRDNZ (1 << 26) 120 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 121 #define SDCARD_PBIASLITE_VMODE (1 << 21) 122 123 #ifndef __ASSEMBLY__ 124 125 struct s32ktimer { 126 unsigned char res[0x10]; 127 unsigned int s32k_cr; /* 0x10 */ 128 }; 129 130 #define DEVICE_TYPE_SHIFT 0x6 131 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 132 133 /* Output impedance control */ 134 #define ds_120_ohm 0x0 135 #define ds_60_ohm 0x1 136 #define ds_45_ohm 0x2 137 #define ds_30_ohm 0x3 138 #define ds_mask 0x3 139 140 /* Slew rate control */ 141 #define sc_slow 0x0 142 #define sc_medium 0x1 143 #define sc_fast 0x2 144 #define sc_na 0x3 145 #define sc_mask 0x3 146 147 /* Target capacitance control */ 148 #define lb_5_12_pf 0x0 149 #define lb_12_25_pf 0x1 150 #define lb_25_50_pf 0x2 151 #define lb_50_80_pf 0x3 152 #define lb_mask 0x3 153 154 #define usb_i_mask 0x7 155 156 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 157 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 158 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 159 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 160 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 161 162 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 163 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 164 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 165 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 166 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 167 168 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 169 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 170 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 171 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC 172 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 173 174 #define EFUSE_1 0x45145100 175 #define EFUSE_2 0x45145100 176 #define EFUSE_3 0x45145100 177 #define EFUSE_4 0x45145100 178 #endif /* __ASSEMBLY__ */ 179 180 /* 181 * In all cases, the TRM defines the RAM Memory Map for the processor 182 * and indicates the area for the downloaded image. We use all of that 183 * space for download and once up and running may use other parts of the 184 * map for our needs. We set a scratch space that is at the end of the 185 * OMAP5 download area, but within the DRA7xx download area (as it is 186 * much larger) and do not, at this time, make use of the additional 187 * space. 188 */ 189 #if defined(CONFIG_DRA7XX) 190 #define NON_SECURE_SRAM_START 0x40300000 191 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 192 #define NON_SECURE_SRAM_IMG_END 0x4037C000 193 #else 194 #define NON_SECURE_SRAM_START 0x40300000 195 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 196 #define NON_SECURE_SRAM_IMG_END 0x4031E000 197 #endif 198 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) 199 200 /* base address for indirect vectors (internal boot mode) */ 201 #define SRAM_ROM_VECT_BASE 0x4031F000 202 203 /* CONTROL_SRCOMP_XXX_SIDE */ 204 #define OVERRIDE_XS_SHIFT 30 205 #define OVERRIDE_XS_MASK (1 << 30) 206 #define SRCODE_READ_XS_SHIFT 12 207 #define SRCODE_READ_XS_MASK (0xff << 12) 208 #define PWRDWN_XS_SHIFT 11 209 #define PWRDWN_XS_MASK (1 << 11) 210 #define DIVIDE_FACTOR_XS_SHIFT 4 211 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 212 #define MULTIPLY_FACTOR_XS_SHIFT 1 213 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 214 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 215 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 216 217 /* ABB settings */ 218 #define OMAP_ABB_SETTLING_TIME 50 219 #define OMAP_ABB_CLOCK_CYCLES 16 220 221 /* ABB tranxdone mask */ 222 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 223 #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) 224 #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) 225 #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) 226 #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) 227 228 /* ABB efuse masks */ 229 #define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) 230 #define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) 231 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) 232 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) 233 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) 234 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) 235 236 #ifndef __ASSEMBLY__ 237 struct srcomp_params { 238 s8 divide_factor; 239 s8 multiply_factor; 240 }; 241 242 struct ctrl_ioregs { 243 u32 ctrl_ddrch; 244 u32 ctrl_lpddr2ch; 245 u32 ctrl_ddr3ch; 246 u32 ctrl_ddrio_0; 247 u32 ctrl_ddrio_1; 248 u32 ctrl_ddrio_2; 249 u32 ctrl_emif_sdram_config_ext; 250 u32 ctrl_emif_sdram_config_ext_final; 251 u32 ctrl_ddr_ctrl_ext_0; 252 }; 253 254 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); 255 256 #endif /* __ASSEMBLY__ */ 257 258 /* Boot parameters */ 259 #ifndef __ASSEMBLY__ 260 struct omap_boot_parameters { 261 unsigned int boot_message; 262 unsigned int boot_device_descriptor; 263 unsigned char boot_device; 264 unsigned char reset_reason; 265 unsigned char ch_flags; 266 }; 267 #endif 268 269 #endif 270