1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef _OMAP5_H_ 29 #define _OMAP5_H_ 30 31 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 32 #include <asm/types.h> 33 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 34 35 /* 36 * L4 Peripherals - L4 Wakeup and L4 Core now 37 */ 38 #define OMAP54XX_L4_CORE_BASE 0x4A000000 39 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 40 #define OMAP54XX_L4_PER_BASE 0x48000000 41 42 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 43 #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF 44 #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START 45 #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END 46 47 /* CONTROL */ 48 #define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) 49 #define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) 50 #define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) 51 52 /* LPDDR2 IO regs. To be verified */ 53 #define LPDDR2_IO_REGS_BASE 0x4A100638 54 55 /* CONTROL_ID_CODE */ 56 #define CONTROL_ID_CODE (CTRL_BASE + 0x204) 57 58 /* To be verified */ 59 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 60 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 61 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 62 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 63 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 64 65 /* STD_FUSE_PROD_ID_1 */ 66 #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) 67 #define PROD_ID_1_SILICON_TYPE_SHIFT 16 68 #define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) 69 70 /* UART */ 71 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 72 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 73 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 74 75 /* General Purpose Timers */ 76 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 77 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 78 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 79 80 /* Watchdog Timer2 - MPU watchdog */ 81 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 82 83 /* 32KTIMER */ 84 #define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) 85 86 /* GPMC */ 87 #define OMAP54XX_GPMC_BASE 0x50000000 88 89 /* SYSTEM CONTROL MODULE */ 90 #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 91 92 /* 93 * Hardware Register Details 94 */ 95 96 /* Watchdog Timer */ 97 #define WD_UNLOCK1 0xAAAA 98 #define WD_UNLOCK2 0x5555 99 100 /* GP Timer */ 101 #define TCLR_ST (0x1 << 0) 102 #define TCLR_AR (0x1 << 1) 103 #define TCLR_PRE (0x1 << 5) 104 105 /* Control Module */ 106 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 107 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 108 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 109 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 110 111 /* LPDDR2 IO regs */ 112 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 113 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 114 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 115 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 116 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 117 118 /* CONTROL_EFUSE_2 */ 119 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 120 121 #define SDCARD_PWRDNZ (1 << 26) 122 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 123 #define SDCARD_BIAS_PWRDNZ (1 << 22) 124 #define SDCARD_PBIASLITE_VMODE (1 << 21) 125 126 #ifndef __ASSEMBLY__ 127 128 struct s32ktimer { 129 unsigned char res[0x10]; 130 unsigned int s32k_cr; /* 0x10 */ 131 }; 132 133 #define DEVICE_TYPE_SHIFT 0x6 134 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 135 #define DEVICE_GP 0x3 136 137 /* Output impedance control */ 138 #define ds_120_ohm 0x0 139 #define ds_60_ohm 0x1 140 #define ds_45_ohm 0x2 141 #define ds_30_ohm 0x3 142 #define ds_mask 0x3 143 144 /* Slew rate control */ 145 #define sc_slow 0x0 146 #define sc_medium 0x1 147 #define sc_fast 0x2 148 #define sc_na 0x3 149 #define sc_mask 0x3 150 151 /* Target capacitance control */ 152 #define lb_5_12_pf 0x0 153 #define lb_12_25_pf 0x1 154 #define lb_25_50_pf 0x2 155 #define lb_50_80_pf 0x3 156 #define lb_mask 0x3 157 158 #define usb_i_mask 0x7 159 160 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 161 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 162 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 163 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 164 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 165 166 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 167 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 168 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 169 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 170 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 171 172 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 173 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 174 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 175 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 176 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 177 178 #define EFUSE_1 0x45145100 179 #define EFUSE_2 0x45145100 180 #define EFUSE_3 0x45145100 181 #define EFUSE_4 0x45145100 182 #endif /* __ASSEMBLY__ */ 183 184 /* 185 * Non-secure SRAM Addresses 186 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 187 * at 0x40304000(EMU base) so that our code works for both EMU and GP 188 */ 189 #define NON_SECURE_SRAM_START 0x40300000 190 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 191 /* base address for indirect vectors (internal boot mode) */ 192 #define SRAM_ROM_VECT_BASE 0x4031F000 193 194 #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START 195 /* 196 * SRAM scratch space entries 197 */ 198 #define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR 199 #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) 200 #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) 201 #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) 202 #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) 203 #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) 204 #define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) 205 #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) 206 207 /* Silicon revisions */ 208 #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF 209 #define OMAP4430_ES1_0 0x44300100 210 #define OMAP4430_ES2_0 0x44300200 211 #define OMAP4430_ES2_1 0x44300210 212 #define OMAP4430_ES2_2 0x44300220 213 #define OMAP4430_ES2_3 0x44300230 214 #define OMAP4460_ES1_0 0x44600100 215 #define OMAP4460_ES1_1 0x44600110 216 217 /* ROM code defines */ 218 /* Boot device */ 219 #define BOOT_DEVICE_MASK 0xFF 220 #define BOOT_DEVICE_OFFSET 0x8 221 #define DEV_DESC_PTR_OFFSET 0x4 222 #define DEV_DATA_PTR_OFFSET 0x18 223 #define BOOT_MODE_OFFSET 0x8 224 #define RESET_REASON_OFFSET 0x9 225 #define CH_FLAGS_OFFSET 0xA 226 227 #define CH_FLAGS_CHSETTINGS (0x1 << 0) 228 #define CH_FLAGS_CHRAM (0x1 << 1) 229 #define CH_FLAGS_CHFLASH (0x1 << 2) 230 #define CH_FLAGS_CHMMCSD (0x1 << 3) 231 232 /* CONTROL_SRCOMP_XXX_SIDE */ 233 #define OVERRIDE_XS_SHIFT 30 234 #define OVERRIDE_XS_MASK (1 << 30) 235 #define SRCODE_READ_XS_SHIFT 12 236 #define SRCODE_READ_XS_MASK (0xff << 12) 237 #define PWRDWN_XS_SHIFT 11 238 #define PWRDWN_XS_MASK (1 << 11) 239 #define DIVIDE_FACTOR_XS_SHIFT 4 240 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 241 #define MULTIPLY_FACTOR_XS_SHIFT 1 242 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 243 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 244 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 245 246 #ifndef __ASSEMBLY__ 247 struct srcomp_params { 248 s8 divide_factor; 249 s8 multiply_factor; 250 }; 251 252 struct omap_boot_parameters { 253 char *boot_message; 254 unsigned int mem_boot_descriptor; 255 unsigned char omap_bootdevice; 256 unsigned char reset_reason; 257 unsigned char ch_flags; 258 }; 259 260 struct ctrl_ioregs { 261 u32 ctrl_ddrch; 262 u32 ctrl_lpddr2ch; 263 u32 ctrl_ddr3ch; 264 u32 ctrl_ddrio_0; 265 u32 ctrl_ddrio_1; 266 u32 ctrl_ddrio_2; 267 u32 ctrl_emif_sdram_config_ext; 268 }; 269 #endif /* __ASSEMBLY__ */ 270 #endif 271