1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _OMAP5_H_ 13 #define _OMAP5_H_ 14 15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 16 #include <asm/types.h> 17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 18 19 #include <linux/sizes.h> 20 21 /* 22 * L4 Peripherals - L4 Wakeup and L4 Core now 23 */ 24 #define OMAP54XX_L4_CORE_BASE 0x4A000000 25 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 26 #define OMAP54XX_L4_PER_BASE 0x48000000 27 28 /* CONTROL ID CODE */ 29 #define CONTROL_CORE_ID_CODE 0x4A002204 30 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 31 32 #if defined(CONFIG_DRA7XX) 33 #define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE 34 #else 35 #define CONTROL_ID_CODE CONTROL_CORE_ID_CODE 36 #endif 37 38 #if defined(CONFIG_DRA7XX) 39 #define DRA7_USB_OTG_SS1_BASE 0x48890000 40 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000 41 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00 42 #define DRA7_USB3_PHY1_POWER 0x4A002370 43 #define DRA7_USB2_PHY1_POWER 0x4A002300 44 45 #define DRA7_USB_OTG_SS2_BASE 0x488D0000 46 #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000 47 #define DRA7_USB2_PHY2_POWER 0x4A002E74 48 #else 49 #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000 50 #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000 51 #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00 52 #define OMAP5XX_USB3_PHY_POWER 0x4A002370 53 #define OMAP5XX_USB2_PHY_POWER 0x4A002300 54 #endif 55 56 /* To be verified */ 57 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F 58 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F 59 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F 60 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F 61 #define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F 62 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F 63 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F 64 #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F 65 #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F 66 #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F 67 #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F 68 69 #define DRA762_ABZ_PACKAGE 0x2 70 #define DRA762_ACD_PACKAGE 0x3 71 72 /* UART */ 73 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) 74 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) 75 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) 76 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000) 77 78 /* General Purpose Timers */ 79 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) 80 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) 81 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) 82 83 /* Watchdog Timer2 - MPU watchdog */ 84 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) 85 86 /* QSPI */ 87 #define QSPI_BASE 0x4B300000 88 89 /* SATA */ 90 #define DWC_AHSATA_BASE 0x4A140000 91 92 /* 93 * Hardware Register Details 94 */ 95 96 /* Watchdog Timer */ 97 #define WD_UNLOCK1 0xAAAA 98 #define WD_UNLOCK2 0x5555 99 100 /* GP Timer */ 101 #define TCLR_ST (0x1 << 0) 102 #define TCLR_AR (0x1 << 1) 103 #define TCLR_PRE (0x1 << 5) 104 105 /* Control Module */ 106 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 107 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 108 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 109 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 110 111 /* LPDDR2 IO regs */ 112 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 113 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 114 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 115 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 116 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 117 118 /* CONTROL_EFUSE_2 */ 119 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 120 121 #define SDCARD_BIAS_PWRDNZ (1 << 27) 122 #define SDCARD_PWRDNZ (1 << 26) 123 #define SDCARD_BIAS_HIZ_MODE (1 << 25) 124 #define SDCARD_PBIASLITE_VMODE (1 << 21) 125 126 #ifndef __ASSEMBLY__ 127 128 struct s32ktimer { 129 unsigned char res[0x10]; 130 unsigned int s32k_cr; /* 0x10 */ 131 }; 132 133 #define DEVICE_TYPE_SHIFT 0x6 134 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 135 136 /* Output impedance control */ 137 #define ds_120_ohm 0x0 138 #define ds_60_ohm 0x1 139 #define ds_45_ohm 0x2 140 #define ds_30_ohm 0x3 141 #define ds_mask 0x3 142 143 /* Slew rate control */ 144 #define sc_slow 0x0 145 #define sc_medium 0x1 146 #define sc_fast 0x2 147 #define sc_na 0x3 148 #define sc_mask 0x3 149 150 /* Target capacitance control */ 151 #define lb_5_12_pf 0x0 152 #define lb_12_25_pf 0x1 153 #define lb_25_50_pf 0x2 154 #define lb_50_80_pf 0x3 155 #define lb_mask 0x3 156 157 #define usb_i_mask 0x7 158 159 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082 160 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200 161 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421 162 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 163 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 164 165 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C 166 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 167 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 168 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC 169 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 170 171 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C 172 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 173 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 174 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC 175 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 176 177 #define EFUSE_1 0x45145100 178 #define EFUSE_2 0x45145100 179 #define EFUSE_3 0x45145100 180 #define EFUSE_4 0x45145100 181 #endif /* __ASSEMBLY__ */ 182 183 /* 184 * In all cases, the TRM defines the RAM Memory Map for the processor 185 * and indicates the area for the downloaded image. We use all of that 186 * space for download and once up and running may use other parts of the 187 * map for our needs. We set a scratch space that is at the end of the 188 * OMAP5 download area, but within the DRA7xx download area (as it is 189 * much larger) and do not, at this time, make use of the additional 190 * space. 191 */ 192 #if defined(CONFIG_DRA7XX) 193 #define NON_SECURE_SRAM_START 0x40300000 194 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ 195 #define NON_SECURE_SRAM_IMG_END 0x4037C000 196 #else 197 #define NON_SECURE_SRAM_START 0x40300000 198 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ 199 #define NON_SECURE_SRAM_IMG_END 0x4031E000 200 #endif 201 #define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) 202 203 /* base address for indirect vectors (internal boot mode) */ 204 #define SRAM_ROM_VECT_BASE 0x4031F000 205 206 /* CONTROL_SRCOMP_XXX_SIDE */ 207 #define OVERRIDE_XS_SHIFT 30 208 #define OVERRIDE_XS_MASK (1 << 30) 209 #define SRCODE_READ_XS_SHIFT 12 210 #define SRCODE_READ_XS_MASK (0xff << 12) 211 #define PWRDWN_XS_SHIFT 11 212 #define PWRDWN_XS_MASK (1 << 11) 213 #define DIVIDE_FACTOR_XS_SHIFT 4 214 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4) 215 #define MULTIPLY_FACTOR_XS_SHIFT 1 216 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) 217 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 218 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) 219 220 /* ABB settings */ 221 #define OMAP_ABB_SETTLING_TIME 50 222 #define OMAP_ABB_CLOCK_CYCLES 16 223 224 /* ABB tranxdone mask */ 225 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 226 #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31) 227 #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30) 228 #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29) 229 #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) 230 231 /* ABB efuse masks */ 232 #define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) 233 #define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) 234 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) 235 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) 236 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) 237 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) 238 239 #ifndef __ASSEMBLY__ 240 struct srcomp_params { 241 s8 divide_factor; 242 s8 multiply_factor; 243 }; 244 245 struct ctrl_ioregs { 246 u32 ctrl_ddrch; 247 u32 ctrl_lpddr2ch; 248 u32 ctrl_ddr3ch; 249 u32 ctrl_ddrio_0; 250 u32 ctrl_ddrio_1; 251 u32 ctrl_ddrio_2; 252 u32 ctrl_emif_sdram_config_ext; 253 u32 ctrl_emif_sdram_config_ext_final; 254 u32 ctrl_ddr_ctrl_ext_0; 255 }; 256 257 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits); 258 259 #endif /* __ASSEMBLY__ */ 260 261 /* Boot parameters */ 262 #ifndef __ASSEMBLY__ 263 struct omap_boot_parameters { 264 unsigned int boot_message; 265 unsigned int boot_device_descriptor; 266 unsigned char boot_device; 267 unsigned char reset_reason; 268 unsigned char ch_flags; 269 }; 270 #endif 271 272 #endif 273