1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * Authors:
6  *	Aneesh V <aneesh@ti.com>
7  *	Sricharan R <r.sricharan@ti.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef _OMAP5_H_
13 #define _OMAP5_H_
14 
15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
16 #include <asm/types.h>
17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 
19 /*
20  * L4 Peripherals - L4 Wakeup and L4 Core now
21  */
22 #define OMAP54XX_L4_CORE_BASE	0x4A000000
23 #define OMAP54XX_L4_WKUP_BASE	0x4Ae00000
24 #define OMAP54XX_L4_PER_BASE	0x48000000
25 
26 #define OMAP54XX_DRAM_ADDR_SPACE_START	0x80000000
27 #define OMAP54XX_DRAM_ADDR_SPACE_END	0xFFFFFFFF
28 #define DRAM_ADDR_SPACE_START	OMAP54XX_DRAM_ADDR_SPACE_START
29 #define DRAM_ADDR_SPACE_END	OMAP54XX_DRAM_ADDR_SPACE_END
30 
31 /* CONTROL ID CODE */
32 #define CONTROL_CORE_ID_CODE	0x4A002204
33 #define CONTROL_WKUP_ID_CODE	0x4AE0C204
34 
35 #ifdef CONFIG_DRA7XX
36 #define CONTROL_ID_CODE		CONTROL_WKUP_ID_CODE
37 #else
38 #define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
39 #endif
40 
41 /* To be verified */
42 #define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
43 #define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
44 #define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
45 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
46 #define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
47 
48 /* UART */
49 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
50 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
51 #define UART3_BASE		(OMAP54XX_L4_PER_BASE + 0x20000)
52 
53 /* General Purpose Timers */
54 #define GPT1_BASE		(OMAP54XX_L4_WKUP_BASE + 0x18000)
55 #define GPT2_BASE		(OMAP54XX_L4_PER_BASE  + 0x32000)
56 #define GPT3_BASE		(OMAP54XX_L4_PER_BASE  + 0x34000)
57 
58 /* Watchdog Timer2 - MPU watchdog */
59 #define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
60 
61 /* GPMC */
62 #define OMAP54XX_GPMC_BASE	0x50000000
63 
64 /* QSPI */
65 #define QSPI_BASE		0x4B300000
66 
67 /*
68  * Hardware Register Details
69  */
70 
71 /* Watchdog Timer */
72 #define WD_UNLOCK1		0xAAAA
73 #define WD_UNLOCK2		0x5555
74 
75 /* GP Timer */
76 #define TCLR_ST			(0x1 << 0)
77 #define TCLR_AR			(0x1 << 1)
78 #define TCLR_PRE		(0x1 << 5)
79 
80 /* Control Module */
81 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
82 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
83 #define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
84 #define CONTROL_EFUSE_2_OVERRIDE	0x00084000
85 
86 /* LPDDR2 IO regs */
87 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
88 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
89 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
90 #define LPDDR2IO_GR10_WD_MASK				(3 << 17)
91 #define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
92 
93 /* CONTROL_EFUSE_2 */
94 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
95 
96 #define SDCARD_BIAS_PWRDNZ				(1 << 27)
97 #define SDCARD_PWRDNZ					(1 << 26)
98 #define SDCARD_BIAS_HIZ_MODE				(1 << 25)
99 #define SDCARD_PBIASLITE_VMODE				(1 << 21)
100 
101 #ifndef __ASSEMBLY__
102 
103 struct s32ktimer {
104 	unsigned char res[0x10];
105 	unsigned int s32k_cr;	/* 0x10 */
106 };
107 
108 #define DEVICE_TYPE_SHIFT 0x6
109 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
110 #define DEVICE_GP 0x3
111 
112 /* Output impedance control */
113 #define ds_120_ohm	0x0
114 #define ds_60_ohm	0x1
115 #define ds_45_ohm	0x2
116 #define ds_30_ohm	0x3
117 #define ds_mask		0x3
118 
119 /* Slew rate control */
120 #define sc_slow		0x0
121 #define sc_medium	0x1
122 #define sc_fast		0x2
123 #define sc_na		0x3
124 #define sc_mask		0x3
125 
126 /* Target capacitance control */
127 #define lb_5_12_pf	0x0
128 #define lb_12_25_pf	0x1
129 #define lb_25_50_pf	0x2
130 #define lb_50_80_pf	0x3
131 #define lb_mask		0x3
132 
133 #define usb_i_mask	0x7
134 
135 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
136 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
137 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
138 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
139 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
140 
141 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL	0x7C7C7C6C
142 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL	0x64646464
143 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE				0xBAE8C631
144 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE				0xBC6318DC
145 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
146 
147 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
148 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
149 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
150 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
151 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
152 
153 #define EFUSE_1 0x45145100
154 #define EFUSE_2 0x45145100
155 #define EFUSE_3 0x45145100
156 #define EFUSE_4 0x45145100
157 #endif /* __ASSEMBLY__ */
158 
159 /*
160  * In all cases, the TRM defines the RAM Memory Map for the processor
161  * and indicates the area for the downloaded image.  We use all of that
162  * space for download and once up and running may use other parts of the
163  * map for our needs.  We set a scratch space that is at the end of the
164  * OMAP5 download area, but within the DRA7xx download area (as it is
165  * much larger) and do not, at this time, make use of the additional
166  * space.
167  */
168 #ifdef CONFIG_DRA7XX
169 #define NON_SECURE_SRAM_START	0x40300000
170 #define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
171 #else
172 #define NON_SECURE_SRAM_START	0x40300000
173 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
174 #endif
175 #define SRAM_SCRATCH_SPACE_ADDR	0x4031E000
176 
177 /* base address for indirect vectors (internal boot mode) */
178 #define SRAM_ROM_VECT_BASE	0x4031F000
179 
180 /* CONTROL_SRCOMP_XXX_SIDE */
181 #define OVERRIDE_XS_SHIFT		30
182 #define OVERRIDE_XS_MASK		(1 << 30)
183 #define SRCODE_READ_XS_SHIFT		12
184 #define SRCODE_READ_XS_MASK		(0xff << 12)
185 #define PWRDWN_XS_SHIFT			11
186 #define PWRDWN_XS_MASK			(1 << 11)
187 #define DIVIDE_FACTOR_XS_SHIFT		4
188 #define DIVIDE_FACTOR_XS_MASK		(0x7f << 4)
189 #define MULTIPLY_FACTOR_XS_SHIFT	1
190 #define MULTIPLY_FACTOR_XS_MASK		(0x7 << 1)
191 #define SRCODE_OVERRIDE_SEL_XS_SHIFT	0
192 #define SRCODE_OVERRIDE_SEL_XS_MASK	(1 << 0)
193 
194 /* ABB settings */
195 #define OMAP_ABB_SETTLING_TIME		50
196 #define OMAP_ABB_CLOCK_CYCLES		16
197 
198 /* ABB tranxdone mask */
199 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
200 
201 /* ABB efuse masks */
202 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
203 #define OMAP5_ABB_FUSE_ENABLE_MASK		(0x1 << 29)
204 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
205 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
206 
207 /* IO Delay module defines */
208 #define CFG_IO_DELAY_BASE		0x4844A000
209 #define CFG_IO_DELAY_LOCK		(CFG_IO_DELAY_BASE + 0x02C)
210 
211 /* CPSW IO Delay registers*/
212 #define CFG_RGMII0_TXCTL		(CFG_IO_DELAY_BASE + 0x74C)
213 #define CFG_RGMII0_TXD0			(CFG_IO_DELAY_BASE + 0x758)
214 #define CFG_RGMII0_TXD1			(CFG_IO_DELAY_BASE + 0x764)
215 #define CFG_RGMII0_TXD2			(CFG_IO_DELAY_BASE + 0x770)
216 #define CFG_RGMII0_TXD3			(CFG_IO_DELAY_BASE + 0x77C)
217 #define CFG_VIN2A_D13			(CFG_IO_DELAY_BASE + 0xA7C)
218 #define CFG_VIN2A_D17			(CFG_IO_DELAY_BASE + 0xAAC)
219 #define CFG_VIN2A_D16			(CFG_IO_DELAY_BASE + 0xAA0)
220 #define CFG_VIN2A_D15			(CFG_IO_DELAY_BASE + 0xA94)
221 #define CFG_VIN2A_D14			(CFG_IO_DELAY_BASE + 0xA88)
222 
223 #define CFG_IO_DELAY_UNLOCK_KEY		0x0000AAAA
224 #define CFG_IO_DELAY_LOCK_KEY		0x0000AAAB
225 #define CFG_IO_DELAY_ACCESS_PATTERN	0x00029000
226 #define CFG_IO_DELAY_LOCK_MASK		0x400
227 
228 #ifndef __ASSEMBLY__
229 struct srcomp_params {
230 	s8 divide_factor;
231 	s8 multiply_factor;
232 };
233 
234 struct ctrl_ioregs {
235 	u32 ctrl_ddrch;
236 	u32 ctrl_lpddr2ch;
237 	u32 ctrl_ddr3ch;
238 	u32 ctrl_ddrio_0;
239 	u32 ctrl_ddrio_1;
240 	u32 ctrl_ddrio_2;
241 	u32 ctrl_emif_sdram_config_ext;
242 	u32 ctrl_ddr_ctrl_ext_0;
243 };
244 
245 struct io_delay {
246 	u32 addr;
247 	u32 dly;
248 };
249 #endif /* __ASSEMBLY__ */
250 #endif
251