1 /* 2 * (C) Copyright 2004-2009 3 * Texas Instruments Incorporated 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Aneesh V <aneesh@ti.com> 6 * Balaji Krishnamoorthy <balajitk@ti.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 #ifndef _MUX_OMAP5_H_ 11 #define _MUX_OMAP5_H_ 12 13 #include <asm/types.h> 14 15 #ifdef CONFIG_OFF_PADCONF 16 #define OFF_PD (1 << 12) 17 #define OFF_PU (3 << 12) 18 #define OFF_OUT_PTD (0 << 10) 19 #define OFF_OUT_PTU (2 << 10) 20 #define OFF_IN (1 << 10) 21 #define OFF_OUT (0 << 10) 22 #define OFF_EN (1 << 9) 23 #else 24 #define OFF_PD (0 << 12) 25 #define OFF_PU (0 << 12) 26 #define OFF_OUT_PTD (0 << 10) 27 #define OFF_OUT_PTU (0 << 10) 28 #define OFF_IN (0 << 10) 29 #define OFF_OUT (0 << 10) 30 #define OFF_EN (0 << 9) 31 #endif 32 33 #define IEN (1 << 8) 34 #define IDIS (0 << 8) 35 #define PTU (3 << 3) 36 #define PTD (1 << 3) 37 #define EN (1 << 3) 38 #define DIS (0 << 3) 39 40 #define M0 0 41 #define M1 1 42 #define M2 2 43 #define M3 3 44 #define M4 4 45 #define M5 5 46 #define M6 6 47 #define M7 7 48 49 #define SAFE_MODE M7 50 51 #ifdef CONFIG_OFF_PADCONF 52 #define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) 53 #define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) 54 #define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) 55 #define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) 56 #else 57 #define OFF_IN_PD 0 58 #define OFF_IN_PU 0 59 #define OFF_OUT_PD 0 60 #define OFF_OUT_PU 0 61 #endif 62 63 #define CORE_REVISION 0x0000 64 #define CORE_HWINFO 0x0004 65 #define CORE_SYSCONFIG 0x0010 66 #define EMMC_CLK 0x0040 67 #define EMMC_CMD 0x0042 68 #define EMMC_DATA0 0x0044 69 #define EMMC_DATA1 0x0046 70 #define EMMC_DATA2 0x0048 71 #define EMMC_DATA3 0x004a 72 #define EMMC_DATA4 0x004c 73 #define EMMC_DATA5 0x004e 74 #define EMMC_DATA6 0x0050 75 #define EMMC_DATA7 0x0052 76 #define C2C_CLKOUT0 0x0054 77 #define C2C_CLKOUT1 0x0056 78 #define C2C_CLKIN0 0x0058 79 #define C2C_CLKIN1 0x005a 80 #define C2C_DATAIN0 0x005c 81 #define C2C_DATAIN1 0x005e 82 #define C2C_DATAIN2 0x0060 83 #define C2C_DATAIN3 0x0062 84 #define C2C_DATAIN4 0x0064 85 #define C2C_DATAIN5 0x0066 86 #define C2C_DATAIN6 0x0068 87 #define C2C_DATAIN7 0x006a 88 #define C2C_DATAOUT0 0x006c 89 #define C2C_DATAOUT1 0x006e 90 #define C2C_DATAOUT2 0x0070 91 #define C2C_DATAOUT3 0x0072 92 #define C2C_DATAOUT4 0x0074 93 #define C2C_DATAOUT5 0x0076 94 #define C2C_DATAOUT6 0x0078 95 #define C2C_DATAOUT7 0x007a 96 #define C2C_DATA8 0x007c 97 #define C2C_DATA9 0x007e 98 #define C2C_DATA10 0x0080 99 #define C2C_DATA11 0x0082 100 #define C2C_DATA12 0x0084 101 #define C2C_DATA13 0x0086 102 #define C2C_DATA14 0x0088 103 #define C2C_DATA15 0x008a 104 #define LLIA_WAKEREQOUT 0x008c 105 #define LLIB_WAKEREQOUT 0x008e 106 #define HSI1_ACREADY 0x0090 107 #define HSI1_CAREADY 0x0092 108 #define HSI1_ACWAKE 0x0094 109 #define HSI1_CAWAKE 0x0096 110 #define HSI1_ACFLAG 0x0098 111 #define HSI1_ACDATA 0x009a 112 #define HSI1_CAFLAG 0x009c 113 #define HSI1_CADATA 0x009e 114 #define UART1_TX 0x00a0 115 #define UART1_CTS 0x00a2 116 #define UART1_RX 0x00a4 117 #define UART1_RTS 0x00a6 118 #define HSI2_CAREADY 0x00a8 119 #define HSI2_ACREADY 0x00aa 120 #define HSI2_CAWAKE 0x00ac 121 #define HSI2_ACWAKE 0x00ae 122 #define HSI2_CAFLAG 0x00b0 123 #define HSI2_CADATA 0x00b2 124 #define HSI2_ACFLAG 0x00b4 125 #define HSI2_ACDATA 0x00b6 126 #define UART2_RTS 0x00b8 127 #define UART2_CTS 0x00ba 128 #define UART2_RX 0x00bc 129 #define UART2_TX 0x00be 130 #define USBB1_HSIC_STROBE 0x00c0 131 #define USBB1_HSIC_DATA 0x00c2 132 #define USBB2_HSIC_STROBE 0x00c4 133 #define USBB2_HSIC_DATA 0x00c6 134 #define TIMER10_PWM_EVT 0x00c8 135 #define DSIPORTA_TE0 0x00ca 136 #define DSIPORTA_LANE0X 0x00cc 137 #define DSIPORTA_LANE0Y 0x00ce 138 #define DSIPORTA_LANE1X 0x00d0 139 #define DSIPORTA_LANE1Y 0x00d2 140 #define DSIPORTA_LANE2X 0x00d4 141 #define DSIPORTA_LANE2Y 0x00d6 142 #define DSIPORTA_LANE3X 0x00d8 143 #define DSIPORTA_LANE3Y 0x00da 144 #define DSIPORTA_LANE4X 0x00dc 145 #define DSIPORTA_LANE4Y 0x00de 146 #define DSIPORTC_LANE0X 0x00e0 147 #define DSIPORTC_LANE0Y 0x00e2 148 #define DSIPORTC_LANE1X 0x00e4 149 #define DSIPORTC_LANE1Y 0x00e6 150 #define DSIPORTC_LANE2X 0x00e8 151 #define DSIPORTC_LANE2Y 0x00ea 152 #define DSIPORTC_LANE3X 0x00ec 153 #define DSIPORTC_LANE3Y 0x00ee 154 #define DSIPORTC_LANE4X 0x00f0 155 #define DSIPORTC_LANE4Y 0x00f2 156 #define DSIPORTC_TE0 0x00f4 157 #define TIMER9_PWM_EVT 0x00f6 158 #define I2C4_SCL 0x00f8 159 #define I2C4_SDA 0x00fa 160 #define MCSPI2_CLK 0x00fc 161 #define MCSPI2_SIMO 0x00fe 162 #define MCSPI2_SOMI 0x0100 163 #define MCSPI2_CS0 0x0102 164 #define RFBI_DATA15 0x0104 165 #define RFBI_DATA14 0x0106 166 #define RFBI_DATA13 0x0108 167 #define RFBI_DATA12 0x010a 168 #define RFBI_DATA11 0x010c 169 #define RFBI_DATA10 0x010e 170 #define RFBI_DATA9 0x0110 171 #define RFBI_DATA8 0x0112 172 #define RFBI_DATA7 0x0114 173 #define RFBI_DATA6 0x0116 174 #define RFBI_DATA5 0x0118 175 #define RFBI_DATA4 0x011a 176 #define RFBI_DATA3 0x011c 177 #define RFBI_DATA2 0x011e 178 #define RFBI_DATA1 0x0120 179 #define RFBI_DATA0 0x0122 180 #define RFBI_WE 0x0124 181 #define RFBI_CS0 0x0126 182 #define RFBI_A0 0x0128 183 #define RFBI_RE 0x012a 184 #define RFBI_HSYNC0 0x012c 185 #define RFBI_TE_VSYNC0 0x012e 186 #define GPIO6_182 0x0130 187 #define GPIO6_183 0x0132 188 #define GPIO6_184 0x0134 189 #define GPIO6_185 0x0136 190 #define GPIO6_186 0x0138 191 #define GPIO6_187 0x013a 192 #define HDMI_CEC 0x013c 193 #define HDMI_HPD 0x013e 194 #define HDMI_DDC_SCL 0x0140 195 #define HDMI_DDC_SDA 0x0142 196 #define CSIPORTC_LANE0X 0x0144 197 #define CSIPORTC_LANE0Y 0x0146 198 #define CSIPORTC_LANE1X 0x0148 199 #define CSIPORTC_LANE1Y 0x014a 200 #define CSIPORTB_LANE0X 0x014c 201 #define CSIPORTB_LANE0Y 0x014e 202 #define CSIPORTB_LANE1X 0x0150 203 #define CSIPORTB_LANE1Y 0x0152 204 #define CSIPORTB_LANE2X 0x0154 205 #define CSIPORTB_LANE2Y 0x0156 206 #define CSIPORTA_LANE0X 0x0158 207 #define CSIPORTA_LANE0Y 0x015a 208 #define CSIPORTA_LANE1X 0x015c 209 #define CSIPORTA_LANE1Y 0x015e 210 #define CSIPORTA_LANE2X 0x0160 211 #define CSIPORTA_LANE2Y 0x0162 212 #define CSIPORTA_LANE3X 0x0164 213 #define CSIPORTA_LANE3Y 0x0166 214 #define CSIPORTA_LANE4X 0x0168 215 #define CSIPORTA_LANE4Y 0x016a 216 #define CAM_SHUTTER 0x016c 217 #define CAM_STROBE 0x016e 218 #define CAM_GLOBALRESET 0x0170 219 #define TIMER11_PWM_EVT 0x0172 220 #define TIMER5_PWM_EVT 0x0174 221 #define TIMER6_PWM_EVT 0x0176 222 #define TIMER8_PWM_EVT 0x0178 223 #define I2C3_SCL 0x017a 224 #define I2C3_SDA 0x017c 225 #define GPIO8_233 0x017e 226 #define GPIO8_234 0x0180 227 #define ABE_CLKS 0x0182 228 #define ABEDMIC_DIN1 0x0184 229 #define ABEDMIC_DIN2 0x0186 230 #define ABEDMIC_DIN3 0x0188 231 #define ABEDMIC_CLK1 0x018a 232 #define ABEDMIC_CLK2 0x018c 233 #define ABEDMIC_CLK3 0x018e 234 #define ABESLIMBUS1_CLOCK 0x0190 235 #define ABESLIMBUS1_DATA 0x0192 236 #define ABEMCBSP2_DR 0x0194 237 #define ABEMCBSP2_DX 0x0196 238 #define ABEMCBSP2_FSX 0x0198 239 #define ABEMCBSP2_CLKX 0x019a 240 #define ABEMCPDM_UL_DATA 0x019c 241 #define ABEMCPDM_DL_DATA 0x019e 242 #define ABEMCPDM_FRAME 0x01a0 243 #define ABEMCPDM_LB_CLK 0x01a2 244 #define WLSDIO_CLK 0x01a4 245 #define WLSDIO_CMD 0x01a6 246 #define WLSDIO_DATA0 0x01a8 247 #define WLSDIO_DATA1 0x01aa 248 #define WLSDIO_DATA2 0x01ac 249 #define WLSDIO_DATA3 0x01ae 250 #define UART5_RX 0x01b0 251 #define UART5_TX 0x01b2 252 #define UART5_CTS 0x01b4 253 #define UART5_RTS 0x01b6 254 #define I2C2_SCL 0x01b8 255 #define I2C2_SDA 0x01ba 256 #define MCSPI1_CLK 0x01bc 257 #define MCSPI1_SOMI 0x01be 258 #define MCSPI1_SIMO 0x01c0 259 #define MCSPI1_CS0 0x01c2 260 #define MCSPI1_CS1 0x01c4 261 #define I2C5_SCL 0x01c6 262 #define I2C5_SDA 0x01c8 263 #define PERSLIMBUS2_CLOCK 0x01ca 264 #define PERSLIMBUS2_DATA 0x01cc 265 #define UART6_TX 0x01ce 266 #define UART6_RX 0x01d0 267 #define UART6_CTS 0x01d2 268 #define UART6_RTS 0x01d4 269 #define UART3_CTS_RCTX 0x01d6 270 #define UART3_RTS_IRSD 0x01d8 271 #define UART3_TX_IRTX 0x01da 272 #define UART3_RX_IRRX 0x01dc 273 #define USBB3_HSIC_STROBE 0x01de 274 #define USBB3_HSIC_DATA 0x01e0 275 #define SDCARD_CLK 0x01e2 276 #define SDCARD_CMD 0x01e4 277 #define SDCARD_DATA2 0x01e6 278 #define SDCARD_DATA3 0x01e8 279 #define SDCARD_DATA0 0x01ea 280 #define SDCARD_DATA1 0x01ec 281 #define USBD0_HS_DP 0x01ee 282 #define USBD0_HS_DM 0x01f0 283 #define I2C1_PMIC_SCL 0x01f2 284 #define I2C1_PMIC_SDA 0x01f4 285 #define USBD0_SS_RX 0x01f6 286 287 #define LLIA_WAKEREQIN 0x0040 288 #define LLIB_WAKEREQIN 0x0042 289 #define DRM_EMU0 0x0044 290 #define DRM_EMU1 0x0046 291 #define JTAG_NTRST 0x0048 292 #define JTAG_TCK 0x004a 293 #define JTAG_RTCK 0x004c 294 #define JTAG_TMSC 0x004e 295 #define JTAG_TDI 0x0050 296 #define JTAG_TDO 0x0052 297 #define SYS_32K 0x0054 298 #define FREF_CLK_IOREQ 0x0056 299 #define FREF_CLK0_OUT 0x0058 300 #define FREF_CLK1_OUT 0x005a 301 #define FREF_CLK2_OUT 0x005c 302 #define FREF_CLK2_REQ 0x005e 303 #define FREF_CLK1_REQ 0x0060 304 #define SYS_NRESPWRON 0x0062 305 #define SYS_NRESWARM 0x0064 306 #define SYS_PWR_REQ 0x0066 307 #define SYS_NIRQ1 0x0068 308 #define SYS_NIRQ2 0x006a 309 #define SR_PMIC_SCL 0x006c 310 #define SR_PMIC_SDA 0x006e 311 #define SYS_BOOT0 0x0070 312 #define SYS_BOOT1 0x0072 313 #define SYS_BOOT2 0x0074 314 #define SYS_BOOT3 0x0076 315 #define SYS_BOOT4 0x0078 316 #define SYS_BOOT5 0x007a 317 318 #endif /* _MUX_OMAP5_H_ */ 319