1 /*
2  * (C) Copyright 2013
3  * Texas Instruments Incorporated
4  *
5  * Nishant Kamat <nskamat@ti.com>
6  * Lokesh Vutla <lokeshvutla@ti.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 #ifndef _MUX_DRA7XX_H_
11 #define _MUX_DRA7XX_H_
12 
13 #include <asm/types.h>
14 
15 #define FSC	(1 << 19)
16 #define SSC	(0 << 19)
17 
18 #define IEN	(1 << 18)
19 #define IDIS	(0 << 18)
20 
21 #define PTU	(1 << 17)
22 #define PTD	(0 << 17)
23 #define PEN	(1 << 16)
24 #define PDIS	(0 << 16)
25 
26 #define WKEN	(1 << 24)
27 #define WKDIS	(0 << 24)
28 
29 #define PULL_ENA		(0 << 16)
30 #define PULL_DIS		(1 << 16)
31 #define PULL_UP			(1 << 17)
32 #define INPUT_EN		(1 << 18)
33 #define SLEWCONTROL		(1 << 19)
34 
35 /* Active pin states */
36 #define PIN_OUTPUT		(0 | PULL_DIS)
37 #define PIN_OUTPUT_PULLUP	(PULL_UP)
38 #define PIN_OUTPUT_PULLDOWN	(0)
39 #define PIN_INPUT		(INPUT_EN | PULL_DIS)
40 #define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
41 #define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
42 #define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
43 
44 #define M0	0
45 #define M1	1
46 #define M2	2
47 #define M3	3
48 #define M4	4
49 #define M5	5
50 #define M6	6
51 #define M7	7
52 #define M8	8
53 #define M9	9
54 #define M10	10
55 #define M11	11
56 #define M12	12
57 #define M13	13
58 #define M14	14
59 #define M15	15
60 
61 #define MODE_SELECT		(1 << 8)
62 #define DELAYMODE_SHIFT		4
63 
64 #define MANUAL_MODE	MODE_SELECT
65 
66 #define VIRTUAL_MODE0	(MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
67 #define VIRTUAL_MODE1	(MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
68 #define VIRTUAL_MODE2	(MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
69 #define VIRTUAL_MODE3	(MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
70 #define VIRTUAL_MODE4	(MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
71 #define VIRTUAL_MODE5	(MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
72 #define VIRTUAL_MODE6	(MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
73 #define VIRTUAL_MODE7	(MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
74 #define VIRTUAL_MODE8	(MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
75 #define VIRTUAL_MODE9	(MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
76 #define VIRTUAL_MODE10	(MODE_SELECT | (0xa << DELAYMODE_SHIFT))
77 #define VIRTUAL_MODE11	(MODE_SELECT | (0xb << DELAYMODE_SHIFT))
78 #define VIRTUAL_MODE12	(MODE_SELECT | (0xc << DELAYMODE_SHIFT))
79 #define VIRTUAL_MODE13	(MODE_SELECT | (0xd << DELAYMODE_SHIFT))
80 #define VIRTUAL_MODE14	(MODE_SELECT | (0xe << DELAYMODE_SHIFT))
81 #define VIRTUAL_MODE15	(MODE_SELECT | (0xf << DELAYMODE_SHIFT))
82 
83 #define SAFE_MODE	M15
84 
85 #define GPMC_AD0	0x000
86 #define GPMC_AD1	0x004
87 #define GPMC_AD2	0x008
88 #define GPMC_AD3	0x00C
89 #define GPMC_AD4	0x010
90 #define GPMC_AD5	0x014
91 #define GPMC_AD6	0x018
92 #define GPMC_AD7	0x01C
93 #define GPMC_AD8	0x020
94 #define GPMC_AD9	0x024
95 #define GPMC_AD10	0x028
96 #define GPMC_AD11	0x02C
97 #define GPMC_AD12	0x030
98 #define GPMC_AD13	0x034
99 #define GPMC_AD14	0x038
100 #define GPMC_AD15	0x03C
101 #define GPMC_A0		0x040
102 #define GPMC_A1		0x044
103 #define GPMC_A2		0x048
104 #define GPMC_A3		0x04C
105 #define GPMC_A4		0x050
106 #define GPMC_A5		0x054
107 #define GPMC_A6		0x058
108 #define GPMC_A7		0x05C
109 #define GPMC_A8		0x060
110 #define GPMC_A9		0x064
111 #define GPMC_A10	0x068
112 #define GPMC_A11	0x06C
113 #define GPMC_A12	0x070
114 #define GPMC_A13	0x074
115 #define GPMC_A14	0x078
116 #define GPMC_A15	0x07C
117 #define GPMC_A16	0x080
118 #define GPMC_A17	0x084
119 #define GPMC_A18	0x088
120 #define GPMC_A19	0x08C
121 #define GPMC_A20	0x090
122 #define GPMC_A21	0x094
123 #define GPMC_A22	0x098
124 #define GPMC_A23	0x09C
125 #define GPMC_A24	0x0A0
126 #define GPMC_A25	0x0A4
127 #define GPMC_A26	0x0A8
128 #define GPMC_A27	0x0AC
129 #define GPMC_CS1	0x0B0
130 #define GPMC_CS0	0x0B4
131 #define GPMC_CS2	0x0B8
132 #define GPMC_CS3	0x0BC
133 #define GPMC_CLK	0x0C0
134 #define GPMC_ADVN_ALE	0x0C4
135 #define GPMC_OEN_REN	0x0C8
136 #define GPMC_WEN	0x0CC
137 #define GPMC_BEN0	0x0D0
138 #define GPMC_BEN1	0x0D4
139 #define GPMC_WAIT0	0x0D8
140 #define VIN1A_CLK0	0x0DC
141 #define VIN1B_CLK1	0x0E0
142 #define VIN1A_DE0	0x0E4
143 #define VIN1A_FLD0	0x0E8
144 #define VIN1A_HSYNC0	0x0EC
145 #define VIN1A_VSYNC0	0x0F0
146 #define VIN1A_D0	0x0F4
147 #define VIN1A_D1	0x0F8
148 #define VIN1A_D2	0x0FC
149 #define VIN1A_D3	0x100
150 #define VIN1A_D4	0x104
151 #define VIN1A_D5	0x108
152 #define VIN1A_D6	0x10C
153 #define VIN1A_D7	0x110
154 #define VIN1A_D8	0x114
155 #define VIN1A_D9	0x118
156 #define VIN1A_D10	0x11C
157 #define VIN1A_D11	0x120
158 #define VIN1A_D12	0x124
159 #define VIN1A_D13	0x128
160 #define VIN1A_D14	0x12C
161 #define VIN1A_D15	0x130
162 #define VIN1A_D16	0x134
163 #define VIN1A_D17	0x138
164 #define VIN1A_D18	0x13C
165 #define VIN1A_D19	0x140
166 #define VIN1A_D20	0x144
167 #define VIN1A_D21	0x148
168 #define VIN1A_D22	0x14C
169 #define VIN1A_D23	0x150
170 #define VIN2A_CLK0	0x154
171 #define VIN2A_DE0	0x158
172 #define VIN2A_FLD0	0x15C
173 #define VIN2A_HSYNC0	0x160
174 #define VIN2A_VSYNC0	0x164
175 #define VIN2A_D0	0x168
176 #define VIN2A_D1	0x16C
177 #define VIN2A_D2	0x170
178 #define VIN2A_D3	0x174
179 #define VIN2A_D4	0x178
180 #define VIN2A_D5	0x17C
181 #define VIN2A_D6	0x180
182 #define VIN2A_D7	0x184
183 #define VIN2A_D8	0x188
184 #define VIN2A_D9	0x18C
185 #define VIN2A_D10	0x190
186 #define VIN2A_D11	0x194
187 #define VIN2A_D12	0x198
188 #define VIN2A_D13	0x19C
189 #define VIN2A_D14	0x1A0
190 #define VIN2A_D15	0x1A4
191 #define VIN2A_D16	0x1A8
192 #define VIN2A_D17	0x1AC
193 #define VIN2A_D18	0x1B0
194 #define VIN2A_D19	0x1B4
195 #define VIN2A_D20	0x1B8
196 #define VIN2A_D21	0x1BC
197 #define VIN2A_D22	0x1C0
198 #define VIN2A_D23	0x1C4
199 #define VOUT1_CLK	0x1C8
200 #define VOUT1_DE	0x1CC
201 #define VOUT1_FLD	0x1D0
202 #define VOUT1_HSYNC	0x1D4
203 #define VOUT1_VSYNC	0x1D8
204 #define VOUT1_D0	0x1DC
205 #define VOUT1_D1	0x1E0
206 #define VOUT1_D2	0x1E4
207 #define VOUT1_D3	0x1E8
208 #define VOUT1_D4	0x1EC
209 #define VOUT1_D5	0x1F0
210 #define VOUT1_D6	0x1F4
211 #define VOUT1_D7	0x1F8
212 #define VOUT1_D8	0x1FC
213 #define VOUT1_D9	0x200
214 #define VOUT1_D10	0x204
215 #define VOUT1_D11	0x208
216 #define VOUT1_D12	0x20C
217 #define VOUT1_D13	0x210
218 #define VOUT1_D14	0x214
219 #define VOUT1_D15	0x218
220 #define VOUT1_D16	0x21C
221 #define VOUT1_D17	0x220
222 #define VOUT1_D18	0x224
223 #define VOUT1_D19	0x228
224 #define VOUT1_D20	0x22C
225 #define VOUT1_D21	0x230
226 #define VOUT1_D22	0x234
227 #define VOUT1_D23	0x238
228 #define MDIO_MCLK	0x23C
229 #define MDIO_D		0x240
230 #define RMII_MHZ_50_CLK	0x244
231 #define UART3_RXD	0x248
232 #define UART3_TXD	0x24C
233 #define RGMII0_TXC	0x250
234 #define RGMII0_TXCTL	0x254
235 #define RGMII0_TXD3	0x258
236 #define RGMII0_TXD2	0x25C
237 #define RGMII0_TXD1	0x260
238 #define RGMII0_TXD0	0x264
239 #define RGMII0_RXC	0x268
240 #define RGMII0_RXCTL	0x26C
241 #define RGMII0_RXD3	0x270
242 #define RGMII0_RXD2	0x274
243 #define RGMII0_RXD1	0x278
244 #define RGMII0_RXD0	0x27C
245 #define USB1_DRVVBUS	0x280
246 #define USB2_DRVVBUS	0x284
247 #define GPIO6_14	0x288
248 #define GPIO6_15	0x28C
249 #define GPIO6_16	0x290
250 #define XREF_CLK0	0x294
251 #define XREF_CLK1	0x298
252 #define XREF_CLK2	0x29C
253 #define XREF_CLK3	0x2A0
254 #define MCASP1_ACLKX	0x2A4
255 #define MCASP1_FSX	0x2A8
256 #define MCASP1_ACLKR	0x2AC
257 #define MCASP1_FSR	0x2B0
258 #define MCASP1_AXR0	0x2B4
259 #define MCASP1_AXR1	0x2B8
260 #define MCASP1_AXR2	0x2BC
261 #define MCASP1_AXR3	0x2C0
262 #define MCASP1_AXR4	0x2C4
263 #define MCASP1_AXR5	0x2C8
264 #define MCASP1_AXR6	0x2CC
265 #define MCASP1_AXR7	0x2D0
266 #define MCASP1_AXR8	0x2D4
267 #define MCASP1_AXR9	0x2D8
268 #define MCASP1_AXR10	0x2DC
269 #define MCASP1_AXR11	0x2E0
270 #define MCASP1_AXR12	0x2E4
271 #define MCASP1_AXR13	0x2E8
272 #define MCASP1_AXR14	0x2EC
273 #define MCASP1_AXR15	0x2F0
274 #define MCASP2_ACLKX	0x2F4
275 #define MCASP2_FSX	0x2F8
276 #define MCASP2_ACLKR	0x2FC
277 #define MCASP2_FSR	0x300
278 #define MCASP2_AXR0	0x304
279 #define MCASP2_AXR1	0x308
280 #define MCASP2_AXR2	0x30C
281 #define MCASP2_AXR3	0x310
282 #define MCASP2_AXR4	0x314
283 #define MCASP2_AXR5	0x318
284 #define MCASP2_AXR6	0x31C
285 #define MCASP2_AXR7	0x320
286 #define MCASP3_ACLKX	0x324
287 #define MCASP3_FSX	0x328
288 #define MCASP3_AXR0	0x32C
289 #define MCASP3_AXR1	0x330
290 #define MCASP4_ACLKX	0x334
291 #define MCASP4_FSX	0x338
292 #define MCASP4_AXR0	0x33C
293 #define MCASP4_AXR1	0x340
294 #define MCASP5_ACLKX	0x344
295 #define MCASP5_FSX	0x348
296 #define MCASP5_AXR0	0x34C
297 #define MCASP5_AXR1	0x350
298 #define MMC1_CLK	0x354
299 #define MMC1_CMD	0x358
300 #define MMC1_DAT0	0x35C
301 #define MMC1_DAT1	0x360
302 #define MMC1_DAT2	0x364
303 #define MMC1_DAT3	0x368
304 #define MMC1_SDCD	0x36C
305 #define MMC1_SDWP	0x370
306 #define GPIO6_10	0x374
307 #define GPIO6_11	0x378
308 #define MMC3_CLK	0x37C
309 #define MMC3_CMD	0x380
310 #define MMC3_DAT0	0x384
311 #define MMC3_DAT1	0x388
312 #define MMC3_DAT2	0x38C
313 #define MMC3_DAT3	0x390
314 #define MMC3_DAT4	0x394
315 #define MMC3_DAT5	0x398
316 #define MMC3_DAT6	0x39C
317 #define MMC3_DAT7	0x3A0
318 #define SPI1_SCLK	0x3A4
319 #define SPI1_D1		0x3A8
320 #define SPI1_D0		0x3AC
321 #define SPI1_CS0	0x3B0
322 #define SPI1_CS1	0x3B4
323 #define SPI1_CS2	0x3B8
324 #define SPI1_CS3	0x3BC
325 #define SPI2_SCLK	0x3C0
326 #define SPI2_D1		0x3C4
327 #define SPI2_D0		0x3C8
328 #define SPI2_CS0	0x3CC
329 #define DCAN1_TX	0x3D0
330 #define DCAN1_RX	0x3D4
331 #define DCAN2_TX	0x3D8
332 #define DCAN2_RX	0x3DC
333 #define UART1_RXD	0x3E0
334 #define UART1_TXD	0x3E4
335 #define UART1_CTSN	0x3E8
336 #define UART1_RTSN	0x3EC
337 #define UART2_RXD	0x3F0
338 #define UART2_TXD	0x3F4
339 #define UART2_CTSN	0x3F8
340 #define UART2_RTSN	0x3FC
341 #define I2C1_SDA	0x400
342 #define I2C1_SCL	0x404
343 #define I2C2_SDA	0x408
344 #define I2C2_SCL	0x40C
345 #define I2C3_SDA	0x410
346 #define I2C3_SCL	0x414
347 #define WAKEUP0		0x418
348 #define WAKEUP1		0x41C
349 #define WAKEUP2		0x420
350 #define WAKEUP3		0x424
351 #define ON_OFF		0x428
352 #define RTC_PORZ	0x42C
353 #define TMS		0x430
354 #define TDI		0x434
355 #define TDO		0x438
356 #define TCLK		0x43C
357 #define TRSTN		0x440
358 #define RTCK		0x444
359 #define EMU0		0x448
360 #define EMU1		0x44C
361 #define EMU2		0x450
362 #define EMU3		0x454
363 #define EMU4		0x458
364 #define RESETN		0x45C
365 #define NMIN_DSP	0x460
366 #define RSTOUTN		0x464
367 
368 #endif /* _MUX_DRA7XX_H_ */
369