1 /* 2 * (C) Copyright 2006-2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _CPU_H 11 #define _CPU_H 12 13 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 14 #include <asm/types.h> 15 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 16 17 #ifndef __KERNEL_STRICT_NAMES 18 #ifndef __ASSEMBLY__ 19 struct gpmc_cs { 20 u32 config1; /* 0x00 */ 21 u32 config2; /* 0x04 */ 22 u32 config3; /* 0x08 */ 23 u32 config4; /* 0x0C */ 24 u32 config5; /* 0x10 */ 25 u32 config6; /* 0x14 */ 26 u32 config7; /* 0x18 */ 27 u32 nand_cmd; /* 0x1C */ 28 u32 nand_adr; /* 0x20 */ 29 u32 nand_dat; /* 0x24 */ 30 u8 res[8]; /* blow up to 0x30 byte */ 31 }; 32 33 struct gpmc { 34 u8 res1[0x10]; 35 u32 sysconfig; /* 0x10 */ 36 u8 res2[0x4]; 37 u32 irqstatus; /* 0x18 */ 38 u32 irqenable; /* 0x1C */ 39 u8 res3[0x20]; 40 u32 timeout_control; /* 0x40 */ 41 u8 res4[0xC]; 42 u32 config; /* 0x50 */ 43 u32 status; /* 0x54 */ 44 u8 res5[0x8]; /* 0x58 */ 45 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 46 u8 res6[0x14]; /* 0x1E0 */ 47 u32 ecc_config; /* 0x1F4 */ 48 u32 ecc_control; /* 0x1F8 */ 49 u32 ecc_size_config; /* 0x1FC */ 50 u32 ecc1_result; /* 0x200 */ 51 u32 ecc2_result; /* 0x204 */ 52 u32 ecc3_result; /* 0x208 */ 53 u32 ecc4_result; /* 0x20C */ 54 u32 ecc5_result; /* 0x210 */ 55 u32 ecc6_result; /* 0x214 */ 56 u32 ecc7_result; /* 0x218 */ 57 u32 ecc8_result; /* 0x21C */ 58 u32 ecc9_result; /* 0x220 */ 59 }; 60 61 /* Used for board specific gpmc initialization */ 62 extern struct gpmc *gpmc_cfg; 63 64 struct gptimer { 65 u32 tidr; /* 0x00 r */ 66 u8 res1[0xc]; 67 u32 tiocp_cfg; /* 0x10 rw */ 68 u8 res2[0x10]; 69 u32 tisr_raw; /* 0x24 r */ 70 u32 tisr; /* 0x28 rw */ 71 u32 tier; /* 0x2c rw */ 72 u32 ticr; /* 0x30 rw */ 73 u32 twer; /* 0x34 rw */ 74 u32 tclr; /* 0x38 rw */ 75 u32 tcrr; /* 0x3c rw */ 76 u32 tldr; /* 0x40 rw */ 77 u32 ttgr; /* 0x44 rw */ 78 u32 twpc; /* 0x48 r */ 79 u32 tmar; /* 0x4c rw */ 80 u32 tcar1; /* 0x50 r */ 81 u32 tcicr; /* 0x54 rw */ 82 u32 tcar2; /* 0x58 r */ 83 }; 84 #endif /* __ASSEMBLY__ */ 85 #endif /* __KERNEL_STRICT_NAMES */ 86 87 /* enable sys_clk NO-prescale /1 */ 88 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 89 90 /* Watchdog */ 91 #ifndef __KERNEL_STRICT_NAMES 92 #ifndef __ASSEMBLY__ 93 struct watchdog { 94 u8 res1[0x34]; 95 u32 wwps; /* 0x34 r */ 96 u8 res2[0x10]; 97 u32 wspr; /* 0x48 rw */ 98 }; 99 #endif /* __ASSEMBLY__ */ 100 #endif /* __KERNEL_STRICT_NAMES */ 101 102 #define BIT(x) (1 << (x)) 103 104 #define WD_UNLOCK1 0xAAAA 105 #define WD_UNLOCK2 0x5555 106 107 #define TCLR_ST (0x1 << 0) 108 #define TCLR_AR (0x1 << 1) 109 #define TCLR_PRE (0x1 << 5) 110 111 /* GPMC BASE */ 112 #define GPMC_BASE (OMAP54XX_GPMC_BASE) 113 114 /* I2C base */ 115 #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) 116 #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) 117 #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) 118 #define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) 119 #define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) 120 121 /* MUSB base */ 122 #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) 123 124 /* OMAP4 GPIO registers */ 125 #define OMAP_GPIO_REVISION 0x0000 126 #define OMAP_GPIO_SYSCONFIG 0x0010 127 #define OMAP_GPIO_SYSSTATUS 0x0114 128 #define OMAP_GPIO_IRQSTATUS1 0x0118 129 #define OMAP_GPIO_IRQSTATUS2 0x0128 130 #define OMAP_GPIO_IRQENABLE2 0x012c 131 #define OMAP_GPIO_IRQENABLE1 0x011c 132 #define OMAP_GPIO_WAKE_EN 0x0120 133 #define OMAP_GPIO_CTRL 0x0130 134 #define OMAP_GPIO_OE 0x0134 135 #define OMAP_GPIO_DATAIN 0x0138 136 #define OMAP_GPIO_DATAOUT 0x013c 137 #define OMAP_GPIO_LEVELDETECT0 0x0140 138 #define OMAP_GPIO_LEVELDETECT1 0x0144 139 #define OMAP_GPIO_RISINGDETECT 0x0148 140 #define OMAP_GPIO_FALLINGDETECT 0x014c 141 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 142 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 143 #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 144 #define OMAP_GPIO_SETIRQENABLE1 0x0164 145 #define OMAP_GPIO_CLEARWKUENA 0x0180 146 #define OMAP_GPIO_SETWKUENA 0x0184 147 #define OMAP_GPIO_CLEARDATAOUT 0x0190 148 #define OMAP_GPIO_SETDATAOUT 0x0194 149 150 /* 151 * PRCM 152 */ 153 154 /* PRM */ 155 #define PRM_BASE 0x4AE06000 156 #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 157 158 #define PRM_RSTCTRL PRM_DEVICE_BASE 159 #define PRM_RSTCTRL_RESET 0x01 160 #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 161 #define PRM_RSTST_WARM_RESET_MASK 0x7FEA 162 163 /* DRA7XX CPSW Config space */ 164 #define CPSW_BASE 0x48484000 165 #define CPSW_MDIO_BASE 0x48485000 166 167 #endif /* _CPU_H */ 168