1 /* 2 * (C) Copyright 2006-2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _CPU_H 11 #define _CPU_H 12 13 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 14 #include <asm/types.h> 15 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 16 17 #include <asm/arch/hardware.h> 18 19 #ifndef __KERNEL_STRICT_NAMES 20 #ifndef __ASSEMBLY__ 21 struct gptimer { 22 u32 tidr; /* 0x00 r */ 23 u8 res1[0xc]; 24 u32 tiocp_cfg; /* 0x10 rw */ 25 u8 res2[0x10]; 26 u32 tisr_raw; /* 0x24 r */ 27 u32 tisr; /* 0x28 rw */ 28 u32 tier; /* 0x2c rw */ 29 u32 ticr; /* 0x30 rw */ 30 u32 twer; /* 0x34 rw */ 31 u32 tclr; /* 0x38 rw */ 32 u32 tcrr; /* 0x3c rw */ 33 u32 tldr; /* 0x40 rw */ 34 u32 ttgr; /* 0x44 rw */ 35 u32 twpc; /* 0x48 r */ 36 u32 tmar; /* 0x4c rw */ 37 u32 tcar1; /* 0x50 r */ 38 u32 tcicr; /* 0x54 rw */ 39 u32 tcar2; /* 0x58 r */ 40 }; 41 #endif /* __ASSEMBLY__ */ 42 #endif /* __KERNEL_STRICT_NAMES */ 43 44 /* enable sys_clk NO-prescale /1 */ 45 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 46 47 /* Watchdog */ 48 #ifndef __KERNEL_STRICT_NAMES 49 #ifndef __ASSEMBLY__ 50 struct watchdog { 51 u8 res1[0x34]; 52 u32 wwps; /* 0x34 r */ 53 u8 res2[0x10]; 54 u32 wspr; /* 0x48 rw */ 55 }; 56 #endif /* __ASSEMBLY__ */ 57 #endif /* __KERNEL_STRICT_NAMES */ 58 59 #define WD_UNLOCK1 0xAAAA 60 #define WD_UNLOCK2 0x5555 61 62 #define TCLR_ST (0x1 << 0) 63 #define TCLR_AR (0x1 << 1) 64 #define TCLR_PRE (0x1 << 5) 65 66 /* I2C base */ 67 #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) 68 #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) 69 #define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) 70 #define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000) 71 #define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000) 72 73 /* MUSB base */ 74 #define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) 75 76 /* OMAP4 GPIO registers */ 77 #define OMAP_GPIO_REVISION 0x0000 78 #define OMAP_GPIO_SYSCONFIG 0x0010 79 #define OMAP_GPIO_SYSSTATUS 0x0114 80 #define OMAP_GPIO_IRQSTATUS1 0x0118 81 #define OMAP_GPIO_IRQSTATUS2 0x0128 82 #define OMAP_GPIO_IRQENABLE2 0x012c 83 #define OMAP_GPIO_IRQENABLE1 0x011c 84 #define OMAP_GPIO_WAKE_EN 0x0120 85 #define OMAP_GPIO_CTRL 0x0130 86 #define OMAP_GPIO_OE 0x0134 87 #define OMAP_GPIO_DATAIN 0x0138 88 #define OMAP_GPIO_DATAOUT 0x013c 89 #define OMAP_GPIO_LEVELDETECT0 0x0140 90 #define OMAP_GPIO_LEVELDETECT1 0x0144 91 #define OMAP_GPIO_RISINGDETECT 0x0148 92 #define OMAP_GPIO_FALLINGDETECT 0x014c 93 #define OMAP_GPIO_DEBOUNCE_EN 0x0150 94 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154 95 #define OMAP_GPIO_CLEARIRQENABLE1 0x0160 96 #define OMAP_GPIO_SETIRQENABLE1 0x0164 97 #define OMAP_GPIO_CLEARWKUENA 0x0180 98 #define OMAP_GPIO_SETWKUENA 0x0184 99 #define OMAP_GPIO_CLEARDATAOUT 0x0190 100 #define OMAP_GPIO_SETDATAOUT 0x0194 101 102 /* 103 * PRCM 104 */ 105 106 /* PRM */ 107 #define PRM_BASE 0x4AE06000 108 #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 109 110 #define PRM_RSTCTRL PRM_DEVICE_BASE 111 #define PRM_RSTCTRL_RESET 0x01 112 #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) 113 #define PRM_RSTST_WARM_RESET_MASK 0x7FEA 114 115 /* DRA7XX CPSW Config space */ 116 #define CPSW_BASE 0x48484000 117 #define CPSW_MDIO_BASE 0x48485000 118 119 #endif /* _CPU_H */ 120