1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * Sricharan R <r.sricharan@ti.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 #ifndef _CLOCKS_OMAP5_H_ 11 #define _CLOCKS_OMAP5_H_ 12 #include <common.h> 13 #include <asm/omap_common.h> 14 15 /* 16 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 17 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 18 * much more than that) 19 */ 20 #define LDELAY 1000000 21 22 /* CM_DLL_CTRL */ 23 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 24 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 25 #define CM_DLL_CTRL_NO_OVERRIDE 0 26 27 /* CM_CLKMODE_DPLL */ 28 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 29 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 30 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 31 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 32 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 33 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 34 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 35 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 36 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 37 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 38 #define CM_CLKMODE_DPLL_EN_SHIFT 0 39 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 40 41 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 42 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 43 44 #define DPLL_EN_STOP 1 45 #define DPLL_EN_MN_BYPASS 4 46 #define DPLL_EN_LOW_POWER_BYPASS 5 47 #define DPLL_EN_FAST_RELOCK_BYPASS 6 48 #define DPLL_EN_LOCK 7 49 50 /* CM_IDLEST_DPLL fields */ 51 #define ST_DPLL_CLK_MASK 1 52 53 /* SGX */ 54 #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) 55 #define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) 56 57 /* CM_CLKSEL_DPLL */ 58 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 59 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 60 #define CM_CLKSEL_DPLL_M_SHIFT 8 61 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 62 #define CM_CLKSEL_DPLL_N_SHIFT 0 63 #define CM_CLKSEL_DPLL_N_MASK 0x7F 64 #define CM_CLKSEL_DCC_EN_SHIFT 22 65 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 66 67 /* CM_SYS_CLKSEL */ 68 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 69 70 /* CM_CLKSEL_CORE */ 71 #define CLKSEL_CORE_SHIFT 0 72 #define CLKSEL_L3_SHIFT 4 73 #define CLKSEL_L4_SHIFT 8 74 75 #define CLKSEL_CORE_X2_DIV_1 0 76 #define CLKSEL_L3_CORE_DIV_2 1 77 #define CLKSEL_L4_L3_DIV_2 1 78 79 /* CM_ABE_PLL_REF_CLKSEL */ 80 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 81 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 82 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 83 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 84 85 /* CM_CLKSEL_ABE_PLL_SYS */ 86 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 87 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 88 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 89 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 90 91 /* CM_BYPCLK_DPLL_IVA */ 92 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 93 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 94 95 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 96 97 /* CM_SHADOW_FREQ_CONFIG1 */ 98 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 99 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 100 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 101 102 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 103 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 104 105 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 106 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 107 108 /*CM_<clock_domain>__CLKCTRL */ 109 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 110 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 111 112 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 113 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 114 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 115 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 116 117 118 /* CM_<clock_domain>_<module>_CLKCTRL */ 119 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 120 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 121 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 122 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 123 124 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 125 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 126 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 127 128 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 129 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 130 #define MODULE_CLKCTRL_IDLEST_IDLE 2 131 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 132 133 /* CM_L4PER_GPIO4_CLKCTRL */ 134 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 135 136 /* CM_L3INIT_HSMMCn_CLKCTRL */ 137 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 138 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) 139 140 /* CM_WKUP_GPTIMER1_CLKCTRL */ 141 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 142 143 /* CM_CAM_ISS_CLKCTRL */ 144 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 145 146 /* CM_DSS_DSS_CLKCTRL */ 147 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 148 149 /* CM_L3INIT_USBPHY_CLKCTRL */ 150 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 151 152 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */ 153 #define OPTFCLKEN_FUNC48M_CLK (1 << 15) 154 #define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) 155 #define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) 156 #define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) 157 #define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) 158 #define OPTFCLKEN_UTMI_P3_CLK (1 << 10) 159 #define OPTFCLKEN_UTMI_P2_CLK (1 << 9) 160 #define OPTFCLKEN_UTMI_P1_CLK (1 << 8) 161 #define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) 162 #define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) 163 164 /* CM_L3INIT_USB_TLL_HS_CLKCTRL */ 165 #define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) 166 #define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) 167 #define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) 168 169 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 170 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 171 172 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */ 173 #define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) 174 #define OPTFCLKEN_REFCLK960M (1 << 8) 175 176 /* CM_L3INIT_OCP2SCP1_CLKCTRL */ 177 #define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) 178 179 /* CM_MPU_MPU_CLKCTRL */ 180 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 181 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) 182 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 183 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) 184 185 /* CM_WKUPAON_SCRM_CLKCTRL */ 186 #define OPTFCLKEN_SCRM_PER_SHIFT 9 187 #define OPTFCLKEN_SCRM_PER_MASK (1 << 9) 188 #define OPTFCLKEN_SCRM_CORE_SHIFT 8 189 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) 190 191 /* CM_COREAON_IO_SRCOMP_CLKCTRL */ 192 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 193 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) 194 195 /* PRM_RSTTIME */ 196 #define RSTTIME1_SHIFT 0 197 #define RSTTIME1_MASK (0x3ff << 0) 198 199 /* Clock frequencies */ 200 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 201 202 /* PRM_VC_VAL_BYPASS */ 203 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 204 205 /* CTRL_CORE_SRCOMP_NORTH_SIDE */ 206 #define USB2PHY_DISCHGDET (1 << 29) 207 #define USB2PHY_AUTORESUME_EN (1 << 30) 208 209 /* SMPS */ 210 #define SMPS_I2C_SLAVE_ADDR 0x12 211 #define SMPS_REG_ADDR_12_MPU 0x23 212 #define SMPS_REG_ADDR_45_IVA 0x2B 213 #define SMPS_REG_ADDR_8_CORE 0x37 214 215 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ 216 /* ES1.0 settings */ 217 #define VDD_MPU 1040 218 #define VDD_MM 1040 219 #define VDD_CORE 1040 220 221 #define VDD_MPU_LOW 890 222 #define VDD_MM_LOW 890 223 #define VDD_CORE_LOW 890 224 225 /* ES2.0 settings */ 226 #define VDD_MPU_ES2 1060 227 #define VDD_MM_ES2 1025 228 #define VDD_CORE_ES2 1040 229 230 #define VDD_MPU_ES2_HIGH 1250 231 #define VDD_MM_ES2_OD 1120 232 233 #define VDD_MPU_ES2_LOW 880 234 #define VDD_MM_ES2_LOW 880 235 236 /* TPS659038 Voltage settings in mv for OPP_NOMINAL */ 237 #define VDD_MPU_DRA752 1090 238 #define VDD_EVE_DRA752 1060 239 #define VDD_GPU_DRA752 1060 240 #define VDD_CORE_DRA752 1030 241 #define VDD_IVA_DRA752 1060 242 243 /* Efuse register offsets for DRA7xx platform */ 244 #define DRA752_EFUSE_BASE 0x4A002000 245 #define DRA752_EFUSE_REGBITS 16 246 /* STD_FUSE_OPP_VMIN_IVA_2 */ 247 #define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) 248 /* STD_FUSE_OPP_VMIN_IVA_3 */ 249 #define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) 250 /* STD_FUSE_OPP_VMIN_IVA_4 */ 251 #define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) 252 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */ 253 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) 254 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */ 255 #define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) 256 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */ 257 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) 258 /* STD_FUSE_OPP_VMIN_CORE_2 */ 259 #define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) 260 /* STD_FUSE_OPP_VMIN_GPU_2 */ 261 #define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) 262 /* STD_FUSE_OPP_VMIN_GPU_3 */ 263 #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) 264 /* STD_FUSE_OPP_VMIN_GPU_4 */ 265 #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) 266 /* STD_FUSE_OPP_VMIN_MPU_2 */ 267 #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) 268 /* STD_FUSE_OPP_VMIN_MPU_3 */ 269 #define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) 270 /* STD_FUSE_OPP_VMIN_MPU_4 */ 271 #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) 272 273 /* Standard offset is 0.5v expressed in uv */ 274 #define PALMAS_SMPS_BASE_VOLT_UV 500000 275 276 /* TPS659038 */ 277 #define TPS659038_I2C_SLAVE_ADDR 0x58 278 #define TPS659038_REG_ADDR_SMPS12_MPU 0x23 279 #define TPS659038_REG_ADDR_SMPS45_EVE 0x2B 280 #define TPS659038_REG_ADDR_SMPS6_GPU 0x2F 281 #define TPS659038_REG_ADDR_SMPS7_CORE 0x33 282 #define TPS659038_REG_ADDR_SMPS8_IVA 0x37 283 284 /* TPS */ 285 #define TPS62361_I2C_SLAVE_ADDR 0x60 286 #define TPS62361_REG_ADDR_SET0 0x0 287 #define TPS62361_REG_ADDR_SET1 0x1 288 #define TPS62361_REG_ADDR_SET2 0x2 289 #define TPS62361_REG_ADDR_SET3 0x3 290 #define TPS62361_REG_ADDR_CTRL 0x4 291 #define TPS62361_REG_ADDR_TEMP 0x5 292 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 293 #define TPS62361_REG_ADDR_CHIP_ID 0x8 294 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 295 296 #define TPS62361_BASE_VOLT_MV 500 297 #define TPS62361_VSEL0_GPIO 7 298 299 /* Defines for DPLL setup */ 300 #define DPLL_LOCKED_FREQ_TOLERANCE_0 0 301 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 302 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 303 304 #define DPLL_NO_LOCK 0 305 #define DPLL_LOCK 1 306 307 /* 308 * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. 309 * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles 310 * into microsec and passing the value. 311 */ 312 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 313 314 #ifdef CONFIG_DRA7XX 315 #define V_OSCK 20000000 /* Clock output from T2 */ 316 #else 317 #define V_OSCK 19200000 /* Clock output from T2 */ 318 #endif 319 320 #define V_SCLK V_OSCK 321 322 /* AUXCLKx reg fields */ 323 #define AUXCLK_ENABLE_MASK (1 << 8) 324 #define AUXCLK_SRCSELECT_SHIFT 1 325 #define AUXCLK_SRCSELECT_MASK (3 << 1) 326 #define AUXCLK_CLKDIV_SHIFT 16 327 #define AUXCLK_CLKDIV_MASK (0xF << 16) 328 329 #define AUXCLK_SRCSELECT_SYS_CLK 0 330 #define AUXCLK_SRCSELECT_CORE_DPLL 1 331 #define AUXCLK_SRCSELECT_PER_DPLL 2 332 #define AUXCLK_SRCSELECT_ALTERNATE 3 333 334 #endif /* _CLOCKS_OMAP5_H_ */ 335