1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * Sricharan R <r.sricharan@ti.com> 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 #ifndef _CLOCKS_OMAP5_H_ 27 #define _CLOCKS_OMAP5_H_ 28 #include <common.h> 29 #include <asm/omap_common.h> 30 31 /* 32 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 33 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 34 * much more than that) 35 */ 36 #define LDELAY 1000000 37 38 /* CM_DLL_CTRL */ 39 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 40 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 41 #define CM_DLL_CTRL_NO_OVERRIDE 0 42 43 /* CM_CLKMODE_DPLL */ 44 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 45 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 46 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 47 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 48 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 49 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 50 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 51 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 52 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 53 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 54 #define CM_CLKMODE_DPLL_EN_SHIFT 0 55 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 56 57 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 58 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 59 60 #define DPLL_EN_STOP 1 61 #define DPLL_EN_MN_BYPASS 4 62 #define DPLL_EN_LOW_POWER_BYPASS 5 63 #define DPLL_EN_FAST_RELOCK_BYPASS 6 64 #define DPLL_EN_LOCK 7 65 66 /* CM_IDLEST_DPLL fields */ 67 #define ST_DPLL_CLK_MASK 1 68 69 /* SGX */ 70 #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) 71 #define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) 72 73 /* CM_CLKSEL_DPLL */ 74 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 75 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 76 #define CM_CLKSEL_DPLL_M_SHIFT 8 77 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 78 #define CM_CLKSEL_DPLL_N_SHIFT 0 79 #define CM_CLKSEL_DPLL_N_MASK 0x7F 80 #define CM_CLKSEL_DCC_EN_SHIFT 22 81 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 82 83 /* CM_SYS_CLKSEL */ 84 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 85 86 /* CM_CLKSEL_CORE */ 87 #define CLKSEL_CORE_SHIFT 0 88 #define CLKSEL_L3_SHIFT 4 89 #define CLKSEL_L4_SHIFT 8 90 91 #define CLKSEL_CORE_X2_DIV_1 0 92 #define CLKSEL_L3_CORE_DIV_2 1 93 #define CLKSEL_L4_L3_DIV_2 1 94 95 /* CM_ABE_PLL_REF_CLKSEL */ 96 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 97 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 98 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 99 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 100 101 /* CM_CLKSEL_ABE_PLL_SYS */ 102 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 103 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 104 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 105 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 106 107 /* CM_BYPCLK_DPLL_IVA */ 108 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 109 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 110 111 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 112 113 /* CM_SHADOW_FREQ_CONFIG1 */ 114 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 115 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 116 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 117 118 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 119 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 120 121 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 122 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 123 124 /*CM_<clock_domain>__CLKCTRL */ 125 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 126 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 127 128 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 129 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 130 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 131 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 132 133 134 /* CM_<clock_domain>_<module>_CLKCTRL */ 135 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 136 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 137 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 138 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 139 140 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 141 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 142 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 143 144 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 145 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 146 #define MODULE_CLKCTRL_IDLEST_IDLE 2 147 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 148 149 /* CM_L4PER_GPIO4_CLKCTRL */ 150 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 151 152 /* CM_L3INIT_HSMMCn_CLKCTRL */ 153 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 154 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) 155 156 /* CM_WKUP_GPTIMER1_CLKCTRL */ 157 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 158 159 /* CM_CAM_ISS_CLKCTRL */ 160 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 161 162 /* CM_DSS_DSS_CLKCTRL */ 163 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 164 165 /* CM_L3INIT_USBPHY_CLKCTRL */ 166 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 167 168 /* CM_MPU_MPU_CLKCTRL */ 169 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 170 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) 171 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 172 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) 173 174 /* CM_WKUPAON_SCRM_CLKCTRL */ 175 #define OPTFCLKEN_SCRM_PER_SHIFT 9 176 #define OPTFCLKEN_SCRM_PER_MASK (1 << 9) 177 #define OPTFCLKEN_SCRM_CORE_SHIFT 8 178 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) 179 180 /* CM_COREAON_IO_SRCOMP_CLKCTRL */ 181 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 182 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) 183 184 /* PRM_RSTTIME */ 185 #define RSTTIME1_SHIFT 0 186 #define RSTTIME1_MASK (0x3ff << 0) 187 188 /* Clock frequencies */ 189 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 190 191 /* PRM_VC_VAL_BYPASS */ 192 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 193 194 /* SMPS */ 195 #define SMPS_I2C_SLAVE_ADDR 0x12 196 #define SMPS_REG_ADDR_12_MPU 0x23 197 #define SMPS_REG_ADDR_45_IVA 0x2B 198 #define SMPS_REG_ADDR_8_CORE 0x37 199 200 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ 201 /* ES1.0 settings */ 202 #define VDD_MPU 1040 203 #define VDD_MM 1040 204 #define VDD_CORE 1040 205 206 #define VDD_MPU_LOW 890 207 #define VDD_MM_LOW 890 208 #define VDD_CORE_LOW 890 209 210 /* ES2.0 settings */ 211 #define VDD_MPU_ES2 1060 212 #define VDD_MM_ES2 1025 213 #define VDD_CORE_ES2 1040 214 215 #define VDD_MPU_ES2_HIGH 1250 216 #define VDD_MM_ES2_OD 1120 217 218 #define VDD_MPU_ES2_LOW 880 219 #define VDD_MM_ES2_LOW 880 220 221 /* TPS659038 Voltage settings in mv for OPP_NOMINAL */ 222 #define VDD_MPU_DRA752 1090 223 #define VDD_EVE_DRA752 1060 224 #define VDD_GPU_DRA752 1060 225 #define VDD_CORE_DRA752 1030 226 #define VDD_IVA_DRA752 1060 227 228 /* Efuse register offsets for DRA7xx platform */ 229 #define DRA752_EFUSE_BASE 0x4A002000 230 #define DRA752_EFUSE_REGBITS 16 231 /* STD_FUSE_OPP_VMIN_IVA_2 */ 232 #define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) 233 /* STD_FUSE_OPP_VMIN_IVA_3 */ 234 #define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) 235 /* STD_FUSE_OPP_VMIN_IVA_4 */ 236 #define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) 237 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */ 238 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) 239 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */ 240 #define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) 241 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */ 242 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) 243 /* STD_FUSE_OPP_VMIN_CORE_2 */ 244 #define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) 245 /* STD_FUSE_OPP_VMIN_GPU_2 */ 246 #define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) 247 /* STD_FUSE_OPP_VMIN_GPU_3 */ 248 #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) 249 /* STD_FUSE_OPP_VMIN_GPU_4 */ 250 #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) 251 /* STD_FUSE_OPP_VMIN_MPU_2 */ 252 #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) 253 /* STD_FUSE_OPP_VMIN_MPU_3 */ 254 #define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) 255 /* STD_FUSE_OPP_VMIN_MPU_4 */ 256 #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) 257 258 /* Standard offset is 0.5v expressed in uv */ 259 #define PALMAS_SMPS_BASE_VOLT_UV 500000 260 261 /* TPS659038 */ 262 #define TPS659038_I2C_SLAVE_ADDR 0x58 263 #define TPS659038_REG_ADDR_SMPS12_MPU 0x23 264 #define TPS659038_REG_ADDR_SMPS45_EVE 0x2B 265 #define TPS659038_REG_ADDR_SMPS6_GPU 0x2F 266 #define TPS659038_REG_ADDR_SMPS7_CORE 0x33 267 #define TPS659038_REG_ADDR_SMPS8_IVA 0x37 268 269 /* TPS */ 270 #define TPS62361_I2C_SLAVE_ADDR 0x60 271 #define TPS62361_REG_ADDR_SET0 0x0 272 #define TPS62361_REG_ADDR_SET1 0x1 273 #define TPS62361_REG_ADDR_SET2 0x2 274 #define TPS62361_REG_ADDR_SET3 0x3 275 #define TPS62361_REG_ADDR_CTRL 0x4 276 #define TPS62361_REG_ADDR_TEMP 0x5 277 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 278 #define TPS62361_REG_ADDR_CHIP_ID 0x8 279 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 280 281 #define TPS62361_BASE_VOLT_MV 500 282 #define TPS62361_VSEL0_GPIO 7 283 284 /* Defines for DPLL setup */ 285 #define DPLL_LOCKED_FREQ_TOLERANCE_0 0 286 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 287 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 288 289 #define DPLL_NO_LOCK 0 290 #define DPLL_LOCK 1 291 292 /* 293 * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. 294 * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles 295 * into microsec and passing the value. 296 */ 297 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 298 299 #ifdef CONFIG_DRA7XX 300 #define V_OSCK 20000000 /* Clock output from T2 */ 301 #else 302 #define V_OSCK 19200000 /* Clock output from T2 */ 303 #endif 304 305 #define V_SCLK V_OSCK 306 307 /* AUXCLKx reg fields */ 308 #define AUXCLK_ENABLE_MASK (1 << 8) 309 #define AUXCLK_SRCSELECT_SHIFT 1 310 #define AUXCLK_SRCSELECT_MASK (3 << 1) 311 #define AUXCLK_CLKDIV_SHIFT 16 312 #define AUXCLK_CLKDIV_MASK (0xF << 16) 313 314 #define AUXCLK_SRCSELECT_SYS_CLK 0 315 #define AUXCLK_SRCSELECT_CORE_DPLL 1 316 #define AUXCLK_SRCSELECT_PER_DPLL 2 317 #define AUXCLK_SRCSELECT_ALTERNATE 3 318 319 #endif /* _CLOCKS_OMAP5_H_ */ 320