1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _SYS_PROTO_H_ 9 #define _SYS_PROTO_H_ 10 11 #include <asm/arch/omap.h> 12 #include <asm/arch/clock.h> 13 #include <asm/io.h> 14 #include <asm/omap_common.h> 15 #include <asm/arch/mux_omap4.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; 20 extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; 21 extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; 22 extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; 23 struct omap_sysinfo { 24 char *board_string; 25 }; 26 extern const struct omap_sysinfo sysinfo; 27 28 void gpmc_init(void); 29 void watchdog_init(void); 30 u32 get_device_type(void); 31 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); 32 void set_muxconf_regs_essential(void); 33 void set_muxconf_regs_non_essential(void); 34 void sr32(void *, u32, u32, u32); 35 u32 wait_on_value(u32, u32, void *, u32); 36 void sdelay(unsigned long); 37 void set_pl310_ctrl_reg(u32 val); 38 void setup_clocks_for_console(void); 39 void prcm_init(void); 40 void bypass_dpll(u32 const base); 41 void freq_update_core(void); 42 u32 get_sys_clk_freq(void); 43 u32 omap4_ddr_clk(void); 44 void cancel_out(u32 *num, u32 *den, u32 den_limit); 45 void sdram_init(void); 46 u32 omap_sdram_size(void); 47 u32 cortex_rev(void); 48 void save_omap_boot_params(void); 49 void init_omap_revision(void); 50 void do_io_settings(void); 51 void sri2c_init(void); 52 void gpi2c_init(void); 53 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); 54 u32 warm_reset(void); 55 void force_emif_self_refresh(void); 56 void setup_warmreset_time(void); 57 58 static inline u32 running_from_sdram(void) 59 { 60 u32 pc; 61 asm volatile ("mov %0, pc" : "=r" (pc)); 62 return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && 63 (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); 64 } 65 66 static inline u8 uboot_loaded_by_spl(void) 67 { 68 /* 69 * u-boot can be running from sdram either because of configuration 70 * Header or by SPL. If because of CH, then the romcode sets the 71 * CHSETTINGS executed bit to true in the boot parameter structure that 72 * it passes to the bootloader.This parameter is stored in the ch_flags 73 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a 74 * mandatory section if CH is present. 75 */ 76 if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) 77 return 0; 78 else 79 return running_from_sdram(); 80 } 81 /* 82 * The basic hardware init of OMAP(s_init()) can happen in 4 83 * different contexts: 84 * 1. SPL running from SRAM 85 * 2. U-Boot running from FLASH 86 * 3. Non-XIP U-Boot loaded to SDRAM by SPL 87 * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the 88 * Configuration Header feature 89 * 90 * This function finds this context. 91 * Defining as inline may help in compiling out unused functions in SPL 92 */ 93 static inline u32 omap_hw_init_context(void) 94 { 95 #ifdef CONFIG_SPL_BUILD 96 return OMAP_INIT_CONTEXT_SPL; 97 #else 98 if (uboot_loaded_by_spl()) 99 return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; 100 else if (running_from_sdram()) 101 return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; 102 else 103 return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; 104 #endif 105 } 106 107 #endif 108