1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _SYS_PROTO_H_
9 #define _SYS_PROTO_H_
10 
11 #include <asm/arch/omap.h>
12 #include <asm/arch/clock.h>
13 #include <asm/io.h>
14 #include <asm/omap_common.h>
15 #include <linux/mtd/omap_gpmc.h>
16 #include <asm/arch/mux_omap4.h>
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
21 extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
22 extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
23 extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
24 struct omap_sysinfo {
25 	char *board_string;
26 };
27 extern const struct omap_sysinfo sysinfo;
28 
29 void gpmc_init(void);
30 void watchdog_init(void);
31 u32 get_device_type(void);
32 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
33 void set_muxconf_regs_essential(void);
34 u32 wait_on_value(u32, u32, void *, u32);
35 void sdelay(unsigned long);
36 void set_pl310_ctrl_reg(u32 val);
37 void setup_clocks_for_console(void);
38 void prcm_init(void);
39 void bypass_dpll(u32 const base);
40 void freq_update_core(void);
41 u32 get_sys_clk_freq(void);
42 u32 omap4_ddr_clk(void);
43 void cancel_out(u32 *num, u32 *den, u32 den_limit);
44 void sdram_init(void);
45 u32 omap_sdram_size(void);
46 u32 cortex_rev(void);
47 void save_omap_boot_params(void);
48 void init_omap_revision(void);
49 void do_io_settings(void);
50 void sri2c_init(void);
51 void gpi2c_init(void);
52 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
53 u32 warm_reset(void);
54 void force_emif_self_refresh(void);
55 void setup_warmreset_time(void);
56 
57 static inline u32 running_from_sdram(void)
58 {
59 	u32 pc;
60 	asm volatile ("mov %0, pc" : "=r" (pc));
61 	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
62 	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
63 }
64 
65 static inline u8 uboot_loaded_by_spl(void)
66 {
67 	/*
68 	 * u-boot can be running from sdram either because of configuration
69 	 * Header or by SPL. If because of CH, then the romcode sets the
70 	 * CHSETTINGS executed bit to true in the boot parameter structure that
71 	 * it passes to the bootloader.This parameter is stored in the ch_flags
72 	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
73 	 * mandatory section if CH is present.
74 	 */
75 	if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
76 		return 0;
77 	else
78 		return running_from_sdram();
79 }
80 /*
81  * The basic hardware init of OMAP(s_init()) can happen in 4
82  * different contexts:
83  *  1. SPL running from SRAM
84  *  2. U-Boot running from FLASH
85  *  3. Non-XIP U-Boot loaded to SDRAM by SPL
86  *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
87  *     Configuration Header feature
88  *
89  * This function finds this context.
90  * Defining as inline may help in compiling out unused functions in SPL
91  */
92 static inline u32 omap_hw_init_context(void)
93 {
94 #ifdef CONFIG_SPL_BUILD
95 	return OMAP_INIT_CONTEXT_SPL;
96 #else
97 	if (uboot_loaded_by_spl())
98 		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
99 	else if (running_from_sdram())
100 		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
101 	else
102 		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
103 #endif
104 }
105 
106 #endif
107