1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * 8 * Derived from OMAP3 work by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef _OMAP4_H_ 32 #define _OMAP4_H_ 33 34 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 35 #include <asm/types.h> 36 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 37 38 /* 39 * L4 Peripherals - L4 Wakeup and L4 Core now 40 */ 41 #define OMAP44XX_L4_CORE_BASE 0x4A000000 42 #define OMAP44XX_L4_WKUP_BASE 0x4A300000 43 #define OMAP44XX_L4_PER_BASE 0x48000000 44 45 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 46 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 47 #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 48 #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 49 50 /* CONTROL_ID_CODE */ 51 #define CONTROL_ID_CODE 0x4A002204 52 53 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 54 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 55 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 56 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 57 #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 58 #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F 59 #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F 60 61 /* UART */ 62 #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 63 #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 64 #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 65 66 /* General Purpose Timers */ 67 #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 68 #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 69 #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 70 71 /* Watchdog Timer2 - MPU watchdog */ 72 #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 73 74 /* GPMC */ 75 #define OMAP44XX_GPMC_BASE 0x50000000 76 77 /* 78 * Hardware Register Details 79 */ 80 81 /* Watchdog Timer */ 82 #define WD_UNLOCK1 0xAAAA 83 #define WD_UNLOCK2 0x5555 84 85 /* GP Timer */ 86 #define TCLR_ST (0x1 << 0) 87 #define TCLR_AR (0x1 << 1) 88 #define TCLR_PRE (0x1 << 5) 89 90 /* Control Module */ 91 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 92 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 93 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 94 #define CONTROL_EFUSE_2_OVERRIDE 0x99084000 95 96 /* LPDDR2 IO regs */ 97 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 98 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 99 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 100 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 101 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F 102 103 /* CONTROL_EFUSE_2 */ 104 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 105 106 #define MMC1_PWRDNZ (1 << 26) 107 #define MMC1_PBIASLITE_PWRDNZ (1 << 22) 108 #define MMC1_PBIASLITE_VMODE (1 << 21) 109 110 #ifndef __ASSEMBLY__ 111 112 struct s32ktimer { 113 unsigned char res[0x10]; 114 unsigned int s32k_cr; /* 0x10 */ 115 }; 116 117 #define DEVICE_TYPE_SHIFT (0x8) 118 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) 119 #define DEVICE_GP 0x3 120 121 #endif /* __ASSEMBLY__ */ 122 123 /* 124 * Non-secure SRAM Addresses 125 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 126 * at 0x40304000(EMU base) so that our code works for both EMU and GP 127 */ 128 #define NON_SECURE_SRAM_START 0x40304000 129 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 130 /* base address for indirect vectors (internal boot mode) */ 131 #define SRAM_ROM_VECT_BASE 0x4030D000 132 133 /* ABB settings */ 134 #define OMAP_ABB_SETTLING_TIME 50 135 #define OMAP_ABB_CLOCK_CYCLES 16 136 137 /* ABB tranxdone mask */ 138 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) 139 140 #endif 141