1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Authors: 6 * Aneesh V <aneesh@ti.com> 7 * 8 * Derived from OMAP3 work by 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef _OMAP4_H_ 32 #define _OMAP4_H_ 33 34 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 35 #include <asm/types.h> 36 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 37 38 /* 39 * L4 Peripherals - L4 Wakeup and L4 Core now 40 */ 41 #define OMAP44XX_L4_CORE_BASE 0x4A000000 42 #define OMAP44XX_L4_WKUP_BASE 0x4A300000 43 #define OMAP44XX_L4_PER_BASE 0x48000000 44 45 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 46 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 47 #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START 48 #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END 49 50 /* CONTROL */ 51 #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) 52 #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) 53 #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) 54 55 /* LPDDR2 IO regs */ 56 #define LPDDR2_IO_REGS_BASE 0x4A100638 57 58 /* CONTROL_ID_CODE */ 59 #define CONTROL_ID_CODE 0x4A002204 60 61 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F 62 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F 63 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F 64 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F 65 #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F 66 67 /* UART */ 68 #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) 69 #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) 70 #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) 71 72 /* General Purpose Timers */ 73 #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) 74 #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) 75 #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) 76 77 /* Watchdog Timer2 - MPU watchdog */ 78 #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) 79 80 /* 32KTIMER */ 81 #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) 82 83 /* GPMC */ 84 #define OMAP44XX_GPMC_BASE 0x50000000 85 86 /* SYSTEM CONTROL MODULE */ 87 #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 88 89 /* 90 * Hardware Register Details 91 */ 92 93 /* Watchdog Timer */ 94 #define WD_UNLOCK1 0xAAAA 95 #define WD_UNLOCK2 0x5555 96 97 /* GP Timer */ 98 #define TCLR_ST (0x1 << 0) 99 #define TCLR_AR (0x1 << 1) 100 #define TCLR_PRE (0x1 << 5) 101 102 /* 103 * PRCM 104 */ 105 106 /* PRM */ 107 #define PRM_BASE 0x4A306000 108 #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) 109 110 #define PRM_RSTCTRL PRM_DEVICE_BASE 111 #define PRM_RSTCTRL_RESET 0x01 112 113 /* Control Module */ 114 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) 115 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f 116 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 117 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000 118 119 /* LPDDR2 IO regs */ 120 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C 121 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E 122 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C 123 #define LPDDR2IO_GR10_WD_MASK (3 << 17) 124 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 125 126 /* CONTROL_EFUSE_2 */ 127 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 128 129 #define MMC1_PWRDNZ (1 << 26) 130 #define MMC1_PBIASLITE_PWRDNZ (1 << 22) 131 #define MMC1_PBIASLITE_VMODE (1 << 21) 132 133 #ifndef __ASSEMBLY__ 134 135 struct s32ktimer { 136 unsigned char res[0x10]; 137 unsigned int s32k_cr; /* 0x10 */ 138 }; 139 140 struct omap4_sys_ctrl_regs { 141 unsigned int pad1[129]; 142 unsigned int control_id_code; /* 0x4A002204 */ 143 unsigned int pad11[22]; 144 unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ 145 unsigned int pad2[47]; 146 unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ 147 unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ 148 unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ 149 unsigned int pad3[260277]; 150 unsigned int control_pbiaslite; /* 0x4A100600 */ 151 unsigned int pad4[63]; 152 unsigned int control_efuse_1; /* 0x4A100700 */ 153 unsigned int control_efuse_2; /* 0x4A100704 */ 154 }; 155 156 struct control_lpddr2io_regs { 157 unsigned int control_lpddr2io1_0; 158 unsigned int control_lpddr2io1_1; 159 unsigned int control_lpddr2io1_2; 160 unsigned int control_lpddr2io1_3; 161 unsigned int control_lpddr2io2_0; 162 unsigned int control_lpddr2io2_1; 163 unsigned int control_lpddr2io2_2; 164 unsigned int control_lpddr2io2_3; 165 }; 166 #endif /* __ASSEMBLY__ */ 167 168 /* 169 * Non-secure SRAM Addresses 170 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE 171 * at 0x40304000(EMU base) so that our code works for both EMU and GP 172 */ 173 #define NON_SECURE_SRAM_START 0x40304000 174 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ 175 /* base address for indirect vectors (internal boot mode) */ 176 #define SRAM_ROM_VECT_BASE 0x4030D000 177 /* Temporary SRAM stack used while low level init is done */ 178 #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END 179 #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START 180 /* SRAM scratch space entries */ 181 #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR 182 #define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) 183 #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) 184 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) 185 #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) 186 187 /* ROM code defines */ 188 /* Boot device */ 189 #define BOOT_DEVICE_MASK 0xFF 190 #define BOOT_DEVICE_OFFSET 0x8 191 #define DEV_DESC_PTR_OFFSET 0x4 192 #define DEV_DATA_PTR_OFFSET 0x18 193 #define BOOT_MODE_OFFSET 0x8 194 #define RESET_REASON_OFFSET 0x9 195 #define CH_FLAGS_OFFSET 0xA 196 197 #define CH_FLAGS_CHSETTINGS (0x1 << 0) 198 #define CH_FLAGS_CHRAM (0x1 << 1) 199 #define CH_FLAGS_CHFLASH (0x1 << 2) 200 #define CH_FLAGS_CHMMCSD (0x1 << 3) 201 202 #ifndef __ASSEMBLY__ 203 struct omap_boot_parameters { 204 char *boot_message; 205 unsigned int mem_boot_descriptor; 206 unsigned char omap_bootdevice; 207 unsigned char reset_reason; 208 unsigned char ch_flags; 209 }; 210 #endif 211 #endif 212