1 /*
2  * (C) Copyright 2004-2009
3  * Texas Instruments Incorporated
4  * Richard Woodruff		<r-woodruff2@ti.com>
5  * Aneesh V			<aneesh@ti.com>
6  * Balaji Krishnamoorthy	<balajitk@ti.com>
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 #ifndef _MUX_OMAP4_H_
27 #define _MUX_OMAP4_H_
28 
29 #include <asm/types.h>
30 
31 struct pad_conf_entry {
32 
33 	u16 offset;
34 
35 	u16 val;
36 
37 };
38 
39 #ifdef CONFIG_OFF_PADCONF
40 #define OFF_PD          (1 << 12)
41 #define OFF_PU          (3 << 12)
42 #define OFF_OUT_PTD     (0 << 10)
43 #define OFF_OUT_PTU     (2 << 10)
44 #define OFF_IN          (1 << 10)
45 #define OFF_OUT         (0 << 10)
46 #define OFF_EN          (1 << 9)
47 #else
48 #define OFF_PD          (0 << 12)
49 #define OFF_PU          (0 << 12)
50 #define OFF_OUT_PTD     (0 << 10)
51 #define OFF_OUT_PTU     (0 << 10)
52 #define OFF_IN          (0 << 10)
53 #define OFF_OUT         (0 << 10)
54 #define OFF_EN          (0 << 9)
55 #endif
56 
57 #define IEN             (1 << 8)
58 #define IDIS            (0 << 8)
59 #define PTU             (3 << 3)
60 #define PTD             (1 << 3)
61 #define EN              (1 << 3)
62 #define DIS             (0 << 3)
63 
64 #define M0              0
65 #define M1              1
66 #define M2              2
67 #define M3              3
68 #define M4              4
69 #define M5              5
70 #define M6              6
71 #define M7              7
72 
73 #define SAFE_MODE	M7
74 
75 #ifdef CONFIG_OFF_PADCONF
76 #define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
77 #define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
78 #define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
79 #define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
80 #else
81 #define OFF_IN_PD       0
82 #define OFF_IN_PU       0
83 #define OFF_OUT_PD      0
84 #define OFF_OUT_PU      0
85 #endif
86 
87 #define CORE_REVISION		0x0000
88 #define CORE_HWINFO		0x0004
89 #define CORE_SYSCONFIG		0x0010
90 #define GPMC_AD0		0x0040
91 #define GPMC_AD1		0x0042
92 #define GPMC_AD2		0x0044
93 #define GPMC_AD3		0x0046
94 #define GPMC_AD4		0x0048
95 #define GPMC_AD5		0x004A
96 #define GPMC_AD6		0x004C
97 #define GPMC_AD7		0x004E
98 #define GPMC_AD8		0x0050
99 #define GPMC_AD9		0x0052
100 #define GPMC_AD10		0x0054
101 #define GPMC_AD11		0x0056
102 #define GPMC_AD12		0x0058
103 #define GPMC_AD13		0x005A
104 #define GPMC_AD14		0x005C
105 #define GPMC_AD15		0x005E
106 #define GPMC_A16		0x0060
107 #define GPMC_A17		0x0062
108 #define GPMC_A18		0x0064
109 #define GPMC_A19		0x0066
110 #define GPMC_A20		0x0068
111 #define GPMC_A21		0x006A
112 #define GPMC_A22		0x006C
113 #define GPMC_A23		0x006E
114 #define GPMC_A24		0x0070
115 #define GPMC_A25		0x0072
116 #define GPMC_NCS0		0x0074
117 #define GPMC_NCS1		0x0076
118 #define GPMC_NCS2		0x0078
119 #define GPMC_NCS3		0x007A
120 #define GPMC_NWP		0x007C
121 #define GPMC_CLK		0x007E
122 #define GPMC_NADV_ALE		0x0080
123 #define GPMC_NOE		0x0082
124 #define GPMC_NWE		0x0084
125 #define GPMC_NBE0_CLE		0x0086
126 #define GPMC_NBE1		0x0088
127 #define GPMC_WAIT0		0x008A
128 #define GPMC_WAIT1		0x008C
129 #define C2C_DATA11		0x008E
130 #define C2C_DATA12		0x0090
131 #define C2C_DATA13		0x0092
132 #define C2C_DATA14		0x0094
133 #define C2C_DATA15		0x0096
134 #define HDMI_HPD		0x0098
135 #define HDMI_CEC		0x009A
136 #define HDMI_DDC_SCL		0x009C
137 #define HDMI_DDC_SDA		0x009E
138 #define CSI21_DX0		0x00A0
139 #define CSI21_DY0		0x00A2
140 #define CSI21_DX1		0x00A4
141 #define CSI21_DY1		0x00A6
142 #define CSI21_DX2		0x00A8
143 #define CSI21_DY2		0x00AA
144 #define CSI21_DX3		0x00AC
145 #define CSI21_DY3		0x00AE
146 #define CSI21_DX4		0x00B0
147 #define CSI21_DY4		0x00B2
148 #define CSI22_DX0		0x00B4
149 #define CSI22_DY0		0x00B6
150 #define CSI22_DX1		0x00B8
151 #define CSI22_DY1		0x00BA
152 #define CAM_SHUTTER		0x00BC
153 #define CAM_STROBE		0x00BE
154 #define CAM_GLOBALRESET		0x00C0
155 #define USBB1_ULPITLL_CLK	0x00C2
156 #define USBB1_ULPITLL_STP	0x00C4
157 #define USBB1_ULPITLL_DIR	0x00C6
158 #define USBB1_ULPITLL_NXT	0x00C8
159 #define USBB1_ULPITLL_DAT0	0x00CA
160 #define USBB1_ULPITLL_DAT1	0x00CC
161 #define USBB1_ULPITLL_DAT2	0x00CE
162 #define USBB1_ULPITLL_DAT3	0x00D0
163 #define USBB1_ULPITLL_DAT4	0x00D2
164 #define USBB1_ULPITLL_DAT5	0x00D4
165 #define USBB1_ULPITLL_DAT6	0x00D6
166 #define USBB1_ULPITLL_DAT7	0x00D8
167 #define USBB1_HSIC_DATA		0x00DA
168 #define USBB1_HSIC_STROBE	0x00DC
169 #define USBC1_ICUSB_DP		0x00DE
170 #define USBC1_ICUSB_DM		0x00E0
171 #define SDMMC1_CLK		0x00E2
172 #define SDMMC1_CMD		0x00E4
173 #define SDMMC1_DAT0		0x00E6
174 #define SDMMC1_DAT1		0x00E8
175 #define SDMMC1_DAT2		0x00EA
176 #define SDMMC1_DAT3		0x00EC
177 #define SDMMC1_DAT4		0x00EE
178 #define SDMMC1_DAT5		0x00F0
179 #define SDMMC1_DAT6		0x00F2
180 #define SDMMC1_DAT7		0x00F4
181 #define ABE_MCBSP2_CLKX		0x00F6
182 #define ABE_MCBSP2_DR		0x00F8
183 #define ABE_MCBSP2_DX		0x00FA
184 #define ABE_MCBSP2_FSX		0x00FC
185 #define ABE_MCBSP1_CLKX		0x00FE
186 #define ABE_MCBSP1_DR		0x0100
187 #define ABE_MCBSP1_DX		0x0102
188 #define ABE_MCBSP1_FSX		0x0104
189 #define ABE_PDM_UL_DATA		0x0106
190 #define ABE_PDM_DL_DATA		0x0108
191 #define ABE_PDM_FRAME		0x010A
192 #define ABE_PDM_LB_CLK		0x010C
193 #define ABE_CLKS		0x010E
194 #define ABE_DMIC_CLK1		0x0110
195 #define ABE_DMIC_DIN1		0x0112
196 #define ABE_DMIC_DIN2		0x0114
197 #define ABE_DMIC_DIN3		0x0116
198 #define UART2_CTS		0x0118
199 #define UART2_RTS		0x011A
200 #define UART2_RX		0x011C
201 #define UART2_TX		0x011E
202 #define HDQ_SIO			0x0120
203 #define I2C1_SCL		0x0122
204 #define I2C1_SDA		0x0124
205 #define I2C2_SCL		0x0126
206 #define I2C2_SDA		0x0128
207 #define I2C3_SCL		0x012A
208 #define I2C3_SDA		0x012C
209 #define I2C4_SCL		0x012E
210 #define I2C4_SDA		0x0130
211 #define MCSPI1_CLK		0x0132
212 #define MCSPI1_SOMI		0x0134
213 #define MCSPI1_SIMO		0x0136
214 #define MCSPI1_CS0		0x0138
215 #define MCSPI1_CS1		0x013A
216 #define MCSPI1_CS2		0x013C
217 #define MCSPI1_CS3		0x013E
218 #define UART3_CTS_RCTX		0x0140
219 #define UART3_RTS_SD		0x0142
220 #define UART3_RX_IRRX		0x0144
221 #define UART3_TX_IRTX		0x0146
222 #define SDMMC5_CLK		0x0148
223 #define SDMMC5_CMD		0x014A
224 #define SDMMC5_DAT0		0x014C
225 #define SDMMC5_DAT1		0x014E
226 #define SDMMC5_DAT2		0x0150
227 #define SDMMC5_DAT3		0x0152
228 #define MCSPI4_CLK		0x0154
229 #define MCSPI4_SIMO		0x0156
230 #define MCSPI4_SOMI		0x0158
231 #define MCSPI4_CS0		0x015A
232 #define UART4_RX		0x015C
233 #define UART4_TX		0x015E
234 #define USBB2_ULPITLL_CLK	0x0160
235 #define USBB2_ULPITLL_STP	0x0162
236 #define USBB2_ULPITLL_DIR	0x0164
237 #define USBB2_ULPITLL_NXT	0x0166
238 #define USBB2_ULPITLL_DAT0	0x0168
239 #define USBB2_ULPITLL_DAT1	0x016A
240 #define USBB2_ULPITLL_DAT2	0x016C
241 #define USBB2_ULPITLL_DAT3	0x016E
242 #define USBB2_ULPITLL_DAT4	0x0170
243 #define USBB2_ULPITLL_DAT5	0x0172
244 #define USBB2_ULPITLL_DAT6	0x0174
245 #define USBB2_ULPITLL_DAT7	0x0176
246 #define USBB2_HSIC_DATA		0x0178
247 #define USBB2_HSIC_STROBE	0x017A
248 #define UNIPRO_TX0		0x017C
249 #define UNIPRO_TY0		0x017E
250 #define UNIPRO_TX1		0x0180
251 #define UNIPRO_TY1		0x0182
252 #define UNIPRO_TX2		0x0184
253 #define UNIPRO_TY2		0x0186
254 #define UNIPRO_RX0		0x0188
255 #define UNIPRO_RY0		0x018A
256 #define UNIPRO_RX1		0x018C
257 #define UNIPRO_RY1		0x018E
258 #define UNIPRO_RX2		0x0190
259 #define UNIPRO_RY2		0x0192
260 #define USBA0_OTG_CE		0x0194
261 #define USBA0_OTG_DP		0x0196
262 #define USBA0_OTG_DM		0x0198
263 #define FREF_CLK1_OUT		0x019A
264 #define FREF_CLK2_OUT		0x019C
265 #define SYS_NIRQ1		0x019E
266 #define SYS_NIRQ2		0x01A0
267 #define SYS_BOOT0		0x01A2
268 #define SYS_BOOT1		0x01A4
269 #define SYS_BOOT2		0x01A6
270 #define SYS_BOOT3		0x01A8
271 #define SYS_BOOT4		0x01AA
272 #define SYS_BOOT5		0x01AC
273 #define DPM_EMU0		0x01AE
274 #define DPM_EMU1		0x01B0
275 #define DPM_EMU2		0x01B2
276 #define DPM_EMU3		0x01B4
277 #define DPM_EMU4		0x01B6
278 #define DPM_EMU5		0x01B8
279 #define DPM_EMU6		0x01BA
280 #define DPM_EMU7		0x01BC
281 #define DPM_EMU8		0x01BE
282 #define DPM_EMU9		0x01C0
283 #define DPM_EMU10		0x01C2
284 #define DPM_EMU11		0x01C4
285 #define DPM_EMU12		0x01C6
286 #define DPM_EMU13		0x01C8
287 #define DPM_EMU14		0x01CA
288 #define DPM_EMU15		0x01CC
289 #define DPM_EMU16		0x01CE
290 #define DPM_EMU17		0x01D0
291 #define DPM_EMU18		0x01D2
292 #define DPM_EMU19		0x01D4
293 #define WAKEUPEVENT_0		0x01D8
294 #define WAKEUPEVENT_1		0x01DC
295 #define WAKEUPEVENT_2		0x01E0
296 #define WAKEUPEVENT_3		0x01E4
297 #define WAKEUPEVENT_4		0x01E8
298 #define WAKEUPEVENT_5		0x01EC
299 #define WAKEUPEVENT_6		0x01F0
300 
301 #define WKUP_REVISION		0x0000
302 #define WKUP_HWINFO		0x0004
303 #define WKUP_SYSCONFIG		0x0010
304 #define PAD0_SIM_IO		0x0040
305 #define PAD1_SIM_CLK		0x0042
306 #define PAD0_SIM_RESET		0x0044
307 #define PAD1_SIM_CD		0x0046
308 #define PAD0_SIM_PWRCTRL		0x0048
309 #define PAD1_SR_SCL		0x004A
310 #define PAD0_SR_SDA		0x004C
311 #define PAD1_FREF_XTAL_IN		0x004E
312 #define PAD0_FREF_SLICER_IN	0x0050
313 #define PAD1_FREF_CLK_IOREQ	0x0052
314 #define PAD0_FREF_CLK0_OUT		0x0054
315 #define PAD1_FREF_CLK3_REQ		0x0056
316 #define PAD0_FREF_CLK3_OUT		0x0058
317 #define PAD1_FREF_CLK4_REQ		0x005A
318 #define PAD0_FREF_CLK4_OUT		0x005C
319 #define PAD1_SYS_32K		0x005E
320 #define PAD0_SYS_NRESPWRON		0x0060
321 #define PAD1_SYS_NRESWARM		0x0062
322 #define PAD0_SYS_PWR_REQ		0x0064
323 #define PAD1_SYS_PWRON_RESET	0x0066
324 #define PAD0_SYS_BOOT6		0x0068
325 #define PAD1_SYS_BOOT7		0x006A
326 #define PAD0_JTAG_NTRST		0x006C
327 #define PAD1_JTAG_TCK		0x006D
328 #define PAD0_JTAG_RTCK		0x0070
329 #define PAD1_JTAG_TMS_TMSC		0x0072
330 #define PAD0_JTAG_TDI		0x0074
331 #define PAD1_JTAG_TDO		0x0076
332 #define PADCONF_WAKEUPEVENT_0	0x007C
333 #define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
334 #define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
335 #define PADCONF_MODE		0x05A8
336 #define CONTROL_XTAL_OSCILLATOR			0x05AC
337 #define CONTROL_CONTROL_I2C_2			0x0604
338 #define CONTROL_CONTROL_JTAG			0x0608
339 #define CONTROL_CONTROL_SYS			0x060C
340 #define CONTROL_SPARE_RW		0x0614
341 #define CONTROL_SPARE_R		0x0618
342 #define CONTROL_SPARE_R_C0		0x061C
343 
344 #define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
345 #endif /* _MUX_OMAP4_H_ */
346