1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #ifndef _CLOCKS_OMAP4_H_ 10 #define _CLOCKS_OMAP4_H_ 11 #include <common.h> 12 #include <asm/omap_common.h> 13 14 /* 15 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 16 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 17 * much more than that) 18 */ 19 #define LDELAY 1000000 20 21 /* CM_DLL_CTRL */ 22 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 23 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 24 #define CM_DLL_CTRL_NO_OVERRIDE 0 25 26 /* CM_CLKMODE_DPLL */ 27 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 28 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 29 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 30 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 31 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 32 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 33 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 34 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 35 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 36 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 37 #define CM_CLKMODE_DPLL_EN_SHIFT 0 38 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 39 40 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 41 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 42 43 #define DPLL_EN_STOP 1 44 #define DPLL_EN_MN_BYPASS 4 45 #define DPLL_EN_LOW_POWER_BYPASS 5 46 #define DPLL_EN_FAST_RELOCK_BYPASS 6 47 #define DPLL_EN_LOCK 7 48 49 /* CM_IDLEST_DPLL fields */ 50 #define ST_DPLL_CLK_MASK 1 51 52 /* CM_CLKSEL_DPLL */ 53 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 54 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 55 #define CM_CLKSEL_DPLL_M_SHIFT 8 56 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 57 #define CM_CLKSEL_DPLL_N_SHIFT 0 58 #define CM_CLKSEL_DPLL_N_MASK 0x7F 59 #define CM_CLKSEL_DCC_EN_SHIFT 22 60 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 61 62 /* CM_SYS_CLKSEL */ 63 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 64 65 /* CM_CLKSEL_CORE */ 66 #define CLKSEL_CORE_SHIFT 0 67 #define CLKSEL_L3_SHIFT 4 68 #define CLKSEL_L4_SHIFT 8 69 70 #define CLKSEL_CORE_X2_DIV_1 0 71 #define CLKSEL_L3_CORE_DIV_2 1 72 #define CLKSEL_L4_L3_DIV_2 1 73 74 /* CM_ABE_PLL_REF_CLKSEL */ 75 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 76 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 77 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 78 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 79 80 /* CM_BYPCLK_DPLL_IVA */ 81 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 82 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 83 84 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 85 86 /* CM_SHADOW_FREQ_CONFIG1 */ 87 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 88 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 89 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 90 91 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 92 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 93 94 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 95 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 96 97 /*CM_<clock_domain>__CLKCTRL */ 98 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 99 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 100 101 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 102 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 103 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 104 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 105 106 107 /* CM_<clock_domain>_<module>_CLKCTRL */ 108 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 109 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 110 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 111 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 112 113 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 114 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 115 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 116 117 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 118 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 119 #define MODULE_CLKCTRL_IDLEST_IDLE 2 120 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 121 122 /* CM_L4PER_GPIO4_CLKCTRL */ 123 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 124 125 /* CM_L3INIT_HSMMCn_CLKCTRL */ 126 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 127 128 /* CM_WKUP_GPTIMER1_CLKCTRL */ 129 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 130 131 /* CM_CAM_ISS_CLKCTRL */ 132 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 133 134 /* CM_DSS_DSS_CLKCTRL */ 135 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 136 137 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 138 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 139 140 /* CM_L3INIT_USBPHY_CLKCTRL */ 141 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) 142 143 /* CM_MPU_MPU_CLKCTRL */ 144 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 145 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) 146 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 147 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) 148 149 /* Clock frequencies */ 150 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 151 152 /* PRM_VC_VAL_BYPASS */ 153 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 154 155 /* PMIC */ 156 #define SMPS_I2C_SLAVE_ADDR 0x12 157 /* TWL6030 SMPS */ 158 #define SMPS_REG_ADDR_VCORE1 0x55 159 #define SMPS_REG_ADDR_VCORE2 0x5B 160 #define SMPS_REG_ADDR_VCORE3 0x61 161 /* TWL6032 SMPS */ 162 #define SMPS_REG_ADDR_SMPS1 0x55 163 #define SMPS_REG_ADDR_SMPS2 0x5B 164 #define SMPS_REG_ADDR_SMPS5 0x49 165 166 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 167 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 168 169 /* TPS */ 170 #define TPS62361_I2C_SLAVE_ADDR 0x60 171 #define TPS62361_REG_ADDR_SET0 0x0 172 #define TPS62361_REG_ADDR_SET1 0x1 173 #define TPS62361_REG_ADDR_SET2 0x2 174 #define TPS62361_REG_ADDR_SET3 0x3 175 #define TPS62361_REG_ADDR_CTRL 0x4 176 #define TPS62361_REG_ADDR_TEMP 0x5 177 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 178 #define TPS62361_REG_ADDR_CHIP_ID 0x8 179 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 180 181 #define TPS62361_BASE_VOLT_MV 500 182 #define TPS62361_VSEL0_GPIO 7 183 184 /* AUXCLKx reg fields */ 185 #define AUXCLK_ENABLE_MASK (1 << 8) 186 #define AUXCLK_SRCSELECT_SHIFT 1 187 #define AUXCLK_SRCSELECT_MASK (3 << 1) 188 #define AUXCLK_CLKDIV_SHIFT 16 189 #define AUXCLK_CLKDIV_MASK (0xF << 16) 190 191 #define AUXCLK_SRCSELECT_SYS_CLK 0 192 #define AUXCLK_SRCSELECT_CORE_DPLL 1 193 #define AUXCLK_SRCSELECT_PER_DPLL 2 194 #define AUXCLK_SRCSELECT_ALTERNATE 3 195 196 #define AUXCLK_CLKDIV_2 1 197 #define AUXCLK_CLKDIV_16 0xF 198 199 /* ALTCLKSRC */ 200 #define ALTCLKSRC_MODE_MASK 3 201 #define ALTCLKSRC_ENABLE_INT_MASK 4 202 #define ALTCLKSRC_ENABLE_EXT_MASK 8 203 204 #define ALTCLKSRC_MODE_ACTIVE 1 205 206 #define DPLL_NO_LOCK 0 207 #define DPLL_LOCK 1 208 209 /* Clock Defines */ 210 #define V_OSCK 38400000 /* Clock output from T2 */ 211 #define V_SCLK V_OSCK 212 213 struct omap4_scrm_regs { 214 u32 revision; /* 0x0000 */ 215 u32 pad00[63]; 216 u32 clksetuptime; /* 0x0100 */ 217 u32 pmicsetuptime; /* 0x0104 */ 218 u32 pad01[2]; 219 u32 altclksrc; /* 0x0110 */ 220 u32 pad02[2]; 221 u32 c2cclkm; /* 0x011c */ 222 u32 pad03[56]; 223 u32 extclkreq; /* 0x0200 */ 224 u32 accclkreq; /* 0x0204 */ 225 u32 pwrreq; /* 0x0208 */ 226 u32 pad04[1]; 227 u32 auxclkreq0; /* 0x0210 */ 228 u32 auxclkreq1; /* 0x0214 */ 229 u32 auxclkreq2; /* 0x0218 */ 230 u32 auxclkreq3; /* 0x021c */ 231 u32 auxclkreq4; /* 0x0220 */ 232 u32 auxclkreq5; /* 0x0224 */ 233 u32 pad05[3]; 234 u32 c2cclkreq; /* 0x0234 */ 235 u32 pad06[54]; 236 u32 auxclk0; /* 0x0310 */ 237 u32 auxclk1; /* 0x0314 */ 238 u32 auxclk2; /* 0x0318 */ 239 u32 auxclk3; /* 0x031c */ 240 u32 auxclk4; /* 0x0320 */ 241 u32 auxclk5; /* 0x0324 */ 242 u32 pad07[54]; 243 u32 rsttime_reg; /* 0x0400 */ 244 u32 pad08[6]; 245 u32 c2crstctrl; /* 0x041c */ 246 u32 extpwronrstctrl; /* 0x0420 */ 247 u32 pad09[59]; 248 u32 extwarmrstst_reg; /* 0x0510 */ 249 u32 apewarmrstst_reg; /* 0x0514 */ 250 u32 pad10[1]; 251 u32 c2cwarmrstst_reg; /* 0x051C */ 252 }; 253 #endif /* _CLOCKS_OMAP4_H_ */ 254