1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * 5 * Aneesh V <aneesh@ti.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 #ifndef _CLOCKS_OMAP4_H_ 26 #define _CLOCKS_OMAP4_H_ 27 #include <common.h> 28 #include <asm/omap_common.h> 29 30 /* 31 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 32 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 33 * much more than that) 34 */ 35 #define LDELAY 1000000 36 37 /* CM_DLL_CTRL */ 38 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 39 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 40 #define CM_DLL_CTRL_NO_OVERRIDE 0 41 42 /* CM_CLKMODE_DPLL */ 43 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 44 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 45 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 46 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 47 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 48 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 49 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 50 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 51 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 52 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 53 #define CM_CLKMODE_DPLL_EN_SHIFT 0 54 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 55 56 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 57 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 58 59 #define DPLL_EN_STOP 1 60 #define DPLL_EN_MN_BYPASS 4 61 #define DPLL_EN_LOW_POWER_BYPASS 5 62 #define DPLL_EN_FAST_RELOCK_BYPASS 6 63 #define DPLL_EN_LOCK 7 64 65 /* CM_IDLEST_DPLL fields */ 66 #define ST_DPLL_CLK_MASK 1 67 68 /* CM_CLKSEL_DPLL */ 69 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 70 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 71 #define CM_CLKSEL_DPLL_M_SHIFT 8 72 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 73 #define CM_CLKSEL_DPLL_N_SHIFT 0 74 #define CM_CLKSEL_DPLL_N_MASK 0x7F 75 #define CM_CLKSEL_DCC_EN_SHIFT 22 76 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 77 78 /* CM_SYS_CLKSEL */ 79 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 80 81 /* CM_CLKSEL_CORE */ 82 #define CLKSEL_CORE_SHIFT 0 83 #define CLKSEL_L3_SHIFT 4 84 #define CLKSEL_L4_SHIFT 8 85 86 #define CLKSEL_CORE_X2_DIV_1 0 87 #define CLKSEL_L3_CORE_DIV_2 1 88 #define CLKSEL_L4_L3_DIV_2 1 89 90 /* CM_ABE_PLL_REF_CLKSEL */ 91 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 92 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 93 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 94 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 95 96 /* CM_BYPCLK_DPLL_IVA */ 97 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 98 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 99 100 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 101 102 /* CM_SHADOW_FREQ_CONFIG1 */ 103 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 104 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 105 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 106 107 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 108 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 109 110 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 111 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 112 113 /*CM_<clock_domain>__CLKCTRL */ 114 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 115 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 116 117 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 118 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 119 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 120 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 121 122 123 /* CM_<clock_domain>_<module>_CLKCTRL */ 124 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 125 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 126 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 127 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 128 129 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 130 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 131 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 132 133 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 134 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 135 #define MODULE_CLKCTRL_IDLEST_IDLE 2 136 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 137 138 /* CM_L4PER_GPIO4_CLKCTRL */ 139 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 140 141 /* CM_L3INIT_HSMMCn_CLKCTRL */ 142 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 143 144 /* CM_WKUP_GPTIMER1_CLKCTRL */ 145 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 146 147 /* CM_CAM_ISS_CLKCTRL */ 148 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 149 150 /* CM_DSS_DSS_CLKCTRL */ 151 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 152 153 /* CM_L3INIT_USBPHY_CLKCTRL */ 154 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 155 156 /* CM_MPU_MPU_CLKCTRL */ 157 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 158 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) 159 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 160 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) 161 162 /* Clock frequencies */ 163 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 164 165 /* PRM_VC_VAL_BYPASS */ 166 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 167 168 /* SMPS */ 169 #define SMPS_I2C_SLAVE_ADDR 0x12 170 #define SMPS_REG_ADDR_VCORE1 0x55 171 #define SMPS_REG_ADDR_VCORE2 0x5B 172 #define SMPS_REG_ADDR_VCORE3 0x61 173 174 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 175 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 176 177 /* TPS */ 178 #define TPS62361_I2C_SLAVE_ADDR 0x60 179 #define TPS62361_REG_ADDR_SET0 0x0 180 #define TPS62361_REG_ADDR_SET1 0x1 181 #define TPS62361_REG_ADDR_SET2 0x2 182 #define TPS62361_REG_ADDR_SET3 0x3 183 #define TPS62361_REG_ADDR_CTRL 0x4 184 #define TPS62361_REG_ADDR_TEMP 0x5 185 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 186 #define TPS62361_REG_ADDR_CHIP_ID 0x8 187 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 188 189 #define TPS62361_BASE_VOLT_MV 500 190 #define TPS62361_VSEL0_GPIO 7 191 192 /* AUXCLKx reg fields */ 193 #define AUXCLK_ENABLE_MASK (1 << 8) 194 #define AUXCLK_SRCSELECT_SHIFT 1 195 #define AUXCLK_SRCSELECT_MASK (3 << 1) 196 #define AUXCLK_CLKDIV_SHIFT 16 197 #define AUXCLK_CLKDIV_MASK (0xF << 16) 198 199 #define AUXCLK_SRCSELECT_SYS_CLK 0 200 #define AUXCLK_SRCSELECT_CORE_DPLL 1 201 #define AUXCLK_SRCSELECT_PER_DPLL 2 202 #define AUXCLK_SRCSELECT_ALTERNATE 3 203 204 #define AUXCLK_CLKDIV_2 1 205 #define AUXCLK_CLKDIV_16 0xF 206 207 /* ALTCLKSRC */ 208 #define ALTCLKSRC_MODE_MASK 3 209 #define ALTCLKSRC_ENABLE_INT_MASK 4 210 #define ALTCLKSRC_ENABLE_EXT_MASK 8 211 212 #define ALTCLKSRC_MODE_ACTIVE 1 213 214 #define DPLL_NO_LOCK 0 215 #define DPLL_LOCK 1 216 217 /* Clock Defines */ 218 #define V_OSCK 38400000 /* Clock output from T2 */ 219 #define V_SCLK V_OSCK 220 221 struct omap4_scrm_regs { 222 u32 revision; /* 0x0000 */ 223 u32 pad00[63]; 224 u32 clksetuptime; /* 0x0100 */ 225 u32 pmicsetuptime; /* 0x0104 */ 226 u32 pad01[2]; 227 u32 altclksrc; /* 0x0110 */ 228 u32 pad02[2]; 229 u32 c2cclkm; /* 0x011c */ 230 u32 pad03[56]; 231 u32 extclkreq; /* 0x0200 */ 232 u32 accclkreq; /* 0x0204 */ 233 u32 pwrreq; /* 0x0208 */ 234 u32 pad04[1]; 235 u32 auxclkreq0; /* 0x0210 */ 236 u32 auxclkreq1; /* 0x0214 */ 237 u32 auxclkreq2; /* 0x0218 */ 238 u32 auxclkreq3; /* 0x021c */ 239 u32 auxclkreq4; /* 0x0220 */ 240 u32 auxclkreq5; /* 0x0224 */ 241 u32 pad05[3]; 242 u32 c2cclkreq; /* 0x0234 */ 243 u32 pad06[54]; 244 u32 auxclk0; /* 0x0310 */ 245 u32 auxclk1; /* 0x0314 */ 246 u32 auxclk2; /* 0x0318 */ 247 u32 auxclk3; /* 0x031c */ 248 u32 auxclk4; /* 0x0320 */ 249 u32 auxclk5; /* 0x0324 */ 250 u32 pad07[54]; 251 u32 rsttime_reg; /* 0x0400 */ 252 u32 pad08[6]; 253 u32 c2crstctrl; /* 0x041c */ 254 u32 extpwronrstctrl; /* 0x0420 */ 255 u32 pad09[59]; 256 u32 extwarmrstst_reg; /* 0x0510 */ 257 u32 apewarmrstst_reg; /* 0x0514 */ 258 u32 pad10[1]; 259 u32 c2cwarmrstst_reg; /* 0x051C */ 260 }; 261 #endif /* _CLOCKS_OMAP4_H_ */ 262