1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af1d002fSLokesh Vutla /* 3af1d002fSLokesh Vutla * (C) Copyright 2010 4af1d002fSLokesh Vutla * Texas Instruments, <www.ti.com> 5af1d002fSLokesh Vutla * 6af1d002fSLokesh Vutla * Aneesh V <aneesh@ti.com> 7af1d002fSLokesh Vutla */ 8af1d002fSLokesh Vutla #ifndef _CLOCKS_OMAP4_H_ 9af1d002fSLokesh Vutla #define _CLOCKS_OMAP4_H_ 10af1d002fSLokesh Vutla #include <common.h> 11af1d002fSLokesh Vutla #include <asm/omap_common.h> 12af1d002fSLokesh Vutla 13af1d002fSLokesh Vutla /* 14af1d002fSLokesh Vutla * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 15af1d002fSLokesh Vutla * loop, allow for a minimum of 2 ms wait (in reality the wait will be 16af1d002fSLokesh Vutla * much more than that) 17af1d002fSLokesh Vutla */ 18af1d002fSLokesh Vutla #define LDELAY 1000000 19af1d002fSLokesh Vutla 20af1d002fSLokesh Vutla /* CM_DLL_CTRL */ 21af1d002fSLokesh Vutla #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 22af1d002fSLokesh Vutla #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 23af1d002fSLokesh Vutla #define CM_DLL_CTRL_NO_OVERRIDE 0 24af1d002fSLokesh Vutla 25af1d002fSLokesh Vutla /* CM_CLKMODE_DPLL */ 26af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 27af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 28af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 29af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 30af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 31af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 32af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 33af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 34af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 35af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 36af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_EN_SHIFT 0 37af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 38af1d002fSLokesh Vutla 39af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 40af1d002fSLokesh Vutla #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 41af1d002fSLokesh Vutla 42af1d002fSLokesh Vutla #define DPLL_EN_STOP 1 43af1d002fSLokesh Vutla #define DPLL_EN_MN_BYPASS 4 44af1d002fSLokesh Vutla #define DPLL_EN_LOW_POWER_BYPASS 5 45af1d002fSLokesh Vutla #define DPLL_EN_FAST_RELOCK_BYPASS 6 46af1d002fSLokesh Vutla #define DPLL_EN_LOCK 7 47af1d002fSLokesh Vutla 48af1d002fSLokesh Vutla /* CM_IDLEST_DPLL fields */ 49af1d002fSLokesh Vutla #define ST_DPLL_CLK_MASK 1 50af1d002fSLokesh Vutla 51af1d002fSLokesh Vutla /* CM_CLKSEL_DPLL */ 52af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 53af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 54af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_M_SHIFT 8 55af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 56af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_N_SHIFT 0 57af1d002fSLokesh Vutla #define CM_CLKSEL_DPLL_N_MASK 0x7F 58af1d002fSLokesh Vutla #define CM_CLKSEL_DCC_EN_SHIFT 22 59af1d002fSLokesh Vutla #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 60af1d002fSLokesh Vutla 61af1d002fSLokesh Vutla /* CM_SYS_CLKSEL */ 62af1d002fSLokesh Vutla #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 63af1d002fSLokesh Vutla 64af1d002fSLokesh Vutla /* CM_CLKSEL_CORE */ 65af1d002fSLokesh Vutla #define CLKSEL_CORE_SHIFT 0 66af1d002fSLokesh Vutla #define CLKSEL_L3_SHIFT 4 67af1d002fSLokesh Vutla #define CLKSEL_L4_SHIFT 8 68af1d002fSLokesh Vutla 69af1d002fSLokesh Vutla #define CLKSEL_CORE_X2_DIV_1 0 70af1d002fSLokesh Vutla #define CLKSEL_L3_CORE_DIV_2 1 71af1d002fSLokesh Vutla #define CLKSEL_L4_L3_DIV_2 1 72af1d002fSLokesh Vutla 73af1d002fSLokesh Vutla /* CM_ABE_PLL_REF_CLKSEL */ 74af1d002fSLokesh Vutla #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 75af1d002fSLokesh Vutla #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 76af1d002fSLokesh Vutla #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 77af1d002fSLokesh Vutla #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 78af1d002fSLokesh Vutla 79af1d002fSLokesh Vutla /* CM_BYPCLK_DPLL_IVA */ 80af1d002fSLokesh Vutla #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 81af1d002fSLokesh Vutla #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 82af1d002fSLokesh Vutla 83af1d002fSLokesh Vutla #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 84af1d002fSLokesh Vutla 85af1d002fSLokesh Vutla /* CM_SHADOW_FREQ_CONFIG1 */ 86af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 87af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 88af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 89af1d002fSLokesh Vutla 90af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 91af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 92af1d002fSLokesh Vutla 93af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 94af1d002fSLokesh Vutla #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 95af1d002fSLokesh Vutla 96af1d002fSLokesh Vutla /*CM_<clock_domain>__CLKCTRL */ 97af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 98af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_MASK 3 99af1d002fSLokesh Vutla 100af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 101af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 102af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 103af1d002fSLokesh Vutla #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 104af1d002fSLokesh Vutla 105af1d002fSLokesh Vutla 106af1d002fSLokesh Vutla /* CM_<clock_domain>_<module>_CLKCTRL */ 107af1d002fSLokesh Vutla #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 108af1d002fSLokesh Vutla #define MODULE_CLKCTRL_MODULEMODE_MASK 3 109af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_SHIFT 16 110af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 111af1d002fSLokesh Vutla 112af1d002fSLokesh Vutla #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 113af1d002fSLokesh Vutla #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 114af1d002fSLokesh Vutla #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 115af1d002fSLokesh Vutla 116af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 117af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 118af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_IDLE 2 119af1d002fSLokesh Vutla #define MODULE_CLKCTRL_IDLEST_DISABLED 3 120af1d002fSLokesh Vutla 121af1d002fSLokesh Vutla /* CM_L4PER_GPIO4_CLKCTRL */ 122af1d002fSLokesh Vutla #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 123af1d002fSLokesh Vutla 124af1d002fSLokesh Vutla /* CM_L3INIT_HSMMCn_CLKCTRL */ 125af1d002fSLokesh Vutla #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 126af1d002fSLokesh Vutla 127af1d002fSLokesh Vutla /* CM_WKUP_GPTIMER1_CLKCTRL */ 128af1d002fSLokesh Vutla #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 129af1d002fSLokesh Vutla 130af1d002fSLokesh Vutla /* CM_CAM_ISS_CLKCTRL */ 131af1d002fSLokesh Vutla #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 132af1d002fSLokesh Vutla 133af1d002fSLokesh Vutla /* CM_DSS_DSS_CLKCTRL */ 134af1d002fSLokesh Vutla #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 135af1d002fSLokesh Vutla 1366e495a45SPaul Kocialkowski /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 1376e495a45SPaul Kocialkowski #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 1386e495a45SPaul Kocialkowski 139af1d002fSLokesh Vutla /* CM_L3INIT_USBPHY_CLKCTRL */ 1406e495a45SPaul Kocialkowski #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) 141af1d002fSLokesh Vutla 142af1d002fSLokesh Vutla /* CM_MPU_MPU_CLKCTRL */ 143af1d002fSLokesh Vutla #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 144af1d002fSLokesh Vutla #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) 145af1d002fSLokesh Vutla #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 146af1d002fSLokesh Vutla #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) 147af1d002fSLokesh Vutla 148af1d002fSLokesh Vutla /* Clock frequencies */ 149af1d002fSLokesh Vutla #define OMAP_SYS_CLK_IND_38_4_MHZ 6 150af1d002fSLokesh Vutla 151af1d002fSLokesh Vutla /* PRM_VC_VAL_BYPASS */ 152af1d002fSLokesh Vutla #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 153af1d002fSLokesh Vutla 15440aadf92STaras Kondratiuk /* PMIC */ 155af1d002fSLokesh Vutla #define SMPS_I2C_SLAVE_ADDR 0x12 15640aadf92STaras Kondratiuk /* TWL6030 SMPS */ 157af1d002fSLokesh Vutla #define SMPS_REG_ADDR_VCORE1 0x55 158af1d002fSLokesh Vutla #define SMPS_REG_ADDR_VCORE2 0x5B 159af1d002fSLokesh Vutla #define SMPS_REG_ADDR_VCORE3 0x61 16040aadf92STaras Kondratiuk /* TWL6032 SMPS */ 16140aadf92STaras Kondratiuk #define SMPS_REG_ADDR_SMPS1 0x55 16240aadf92STaras Kondratiuk #define SMPS_REG_ADDR_SMPS2 0x5B 16340aadf92STaras Kondratiuk #define SMPS_REG_ADDR_SMPS5 0x49 164af1d002fSLokesh Vutla 165af1d002fSLokesh Vutla #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 166af1d002fSLokesh Vutla #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 167af1d002fSLokesh Vutla 168af1d002fSLokesh Vutla /* TPS */ 169af1d002fSLokesh Vutla #define TPS62361_I2C_SLAVE_ADDR 0x60 170af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_SET0 0x0 171af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_SET1 0x1 172af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_SET2 0x2 173af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_SET3 0x3 174af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_CTRL 0x4 175af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_TEMP 0x5 176af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_RMP_CTRL 0x6 177af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_CHIP_ID 0x8 178af1d002fSLokesh Vutla #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 179af1d002fSLokesh Vutla 180af1d002fSLokesh Vutla #define TPS62361_BASE_VOLT_MV 500 181af1d002fSLokesh Vutla #define TPS62361_VSEL0_GPIO 7 182af1d002fSLokesh Vutla 183af1d002fSLokesh Vutla /* AUXCLKx reg fields */ 184af1d002fSLokesh Vutla #define AUXCLK_ENABLE_MASK (1 << 8) 185af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_SHIFT 1 186af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_MASK (3 << 1) 187af1d002fSLokesh Vutla #define AUXCLK_CLKDIV_SHIFT 16 188af1d002fSLokesh Vutla #define AUXCLK_CLKDIV_MASK (0xF << 16) 189af1d002fSLokesh Vutla 190af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_SYS_CLK 0 191af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_CORE_DPLL 1 192af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_PER_DPLL 2 193af1d002fSLokesh Vutla #define AUXCLK_SRCSELECT_ALTERNATE 3 194af1d002fSLokesh Vutla 195af1d002fSLokesh Vutla #define AUXCLK_CLKDIV_2 1 196af1d002fSLokesh Vutla #define AUXCLK_CLKDIV_16 0xF 197af1d002fSLokesh Vutla 198af1d002fSLokesh Vutla /* ALTCLKSRC */ 199af1d002fSLokesh Vutla #define ALTCLKSRC_MODE_MASK 3 200af1d002fSLokesh Vutla #define ALTCLKSRC_ENABLE_INT_MASK 4 201af1d002fSLokesh Vutla #define ALTCLKSRC_ENABLE_EXT_MASK 8 202af1d002fSLokesh Vutla 203af1d002fSLokesh Vutla #define ALTCLKSRC_MODE_ACTIVE 1 204af1d002fSLokesh Vutla 205af1d002fSLokesh Vutla #define DPLL_NO_LOCK 0 206af1d002fSLokesh Vutla #define DPLL_LOCK 1 207af1d002fSLokesh Vutla 208f9b814a8SSricharan R /* Clock Defines */ 209f9b814a8SSricharan R #define V_OSCK 38400000 /* Clock output from T2 */ 210f9b814a8SSricharan R #define V_SCLK V_OSCK 211f9b814a8SSricharan R 212af1d002fSLokesh Vutla struct omap4_scrm_regs { 213af1d002fSLokesh Vutla u32 revision; /* 0x0000 */ 214af1d002fSLokesh Vutla u32 pad00[63]; 215af1d002fSLokesh Vutla u32 clksetuptime; /* 0x0100 */ 216af1d002fSLokesh Vutla u32 pmicsetuptime; /* 0x0104 */ 217af1d002fSLokesh Vutla u32 pad01[2]; 218af1d002fSLokesh Vutla u32 altclksrc; /* 0x0110 */ 219af1d002fSLokesh Vutla u32 pad02[2]; 220af1d002fSLokesh Vutla u32 c2cclkm; /* 0x011c */ 221af1d002fSLokesh Vutla u32 pad03[56]; 222af1d002fSLokesh Vutla u32 extclkreq; /* 0x0200 */ 223af1d002fSLokesh Vutla u32 accclkreq; /* 0x0204 */ 224af1d002fSLokesh Vutla u32 pwrreq; /* 0x0208 */ 225af1d002fSLokesh Vutla u32 pad04[1]; 226af1d002fSLokesh Vutla u32 auxclkreq0; /* 0x0210 */ 227af1d002fSLokesh Vutla u32 auxclkreq1; /* 0x0214 */ 228af1d002fSLokesh Vutla u32 auxclkreq2; /* 0x0218 */ 229af1d002fSLokesh Vutla u32 auxclkreq3; /* 0x021c */ 230af1d002fSLokesh Vutla u32 auxclkreq4; /* 0x0220 */ 231af1d002fSLokesh Vutla u32 auxclkreq5; /* 0x0224 */ 232af1d002fSLokesh Vutla u32 pad05[3]; 233af1d002fSLokesh Vutla u32 c2cclkreq; /* 0x0234 */ 234af1d002fSLokesh Vutla u32 pad06[54]; 235af1d002fSLokesh Vutla u32 auxclk0; /* 0x0310 */ 236af1d002fSLokesh Vutla u32 auxclk1; /* 0x0314 */ 237af1d002fSLokesh Vutla u32 auxclk2; /* 0x0318 */ 238af1d002fSLokesh Vutla u32 auxclk3; /* 0x031c */ 239af1d002fSLokesh Vutla u32 auxclk4; /* 0x0320 */ 240af1d002fSLokesh Vutla u32 auxclk5; /* 0x0324 */ 241af1d002fSLokesh Vutla u32 pad07[54]; 242af1d002fSLokesh Vutla u32 rsttime_reg; /* 0x0400 */ 243af1d002fSLokesh Vutla u32 pad08[6]; 244af1d002fSLokesh Vutla u32 c2crstctrl; /* 0x041c */ 245af1d002fSLokesh Vutla u32 extpwronrstctrl; /* 0x0420 */ 246af1d002fSLokesh Vutla u32 pad09[59]; 247af1d002fSLokesh Vutla u32 extwarmrstst_reg; /* 0x0510 */ 248af1d002fSLokesh Vutla u32 apewarmrstst_reg; /* 0x0514 */ 249af1d002fSLokesh Vutla u32 pad10[1]; 250af1d002fSLokesh Vutla u32 c2cwarmrstst_reg; /* 0x051C */ 251af1d002fSLokesh Vutla }; 252af1d002fSLokesh Vutla #endif /* _CLOCKS_OMAP4_H_ */ 253