1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Syed Mohammed Khasim <x0khasim@ti.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 #ifndef _MUX_H_ 22 #define _MUX_H_ 23 24 /* 25 * IEN - Input Enable 26 * IDIS - Input Disable 27 * PTD - Pull type Down 28 * PTU - Pull type Up 29 * DIS - Pull type selection is inactive 30 * EN - Pull type selection is active 31 * M0 - Mode 0 32 */ 33 34 #define IEN (1 << 8) 35 36 #define IDIS (0 << 8) 37 #define PTU (1 << 4) 38 #define PTD (0 << 4) 39 #define EN (1 << 3) 40 #define DIS (0 << 3) 41 42 #define M0 0 43 #define M1 1 44 #define M2 2 45 #define M3 3 46 #define M4 4 47 #define M5 5 48 #define M6 6 49 #define M7 7 50 51 /* 52 * To get the actual address the offset has to added 53 * with OMAP34XX_CTRL_BASE to get the actual address 54 */ 55 56 /*SDRC*/ 57 #define CONTROL_PADCONF_SDRC_D0 0x0030 58 #define CONTROL_PADCONF_SDRC_D1 0x0032 59 #define CONTROL_PADCONF_SDRC_D2 0x0034 60 #define CONTROL_PADCONF_SDRC_D3 0x0036 61 #define CONTROL_PADCONF_SDRC_D4 0x0038 62 #define CONTROL_PADCONF_SDRC_D5 0x003A 63 #define CONTROL_PADCONF_SDRC_D6 0x003C 64 #define CONTROL_PADCONF_SDRC_D7 0x003E 65 #define CONTROL_PADCONF_SDRC_D8 0x0040 66 #define CONTROL_PADCONF_SDRC_D9 0x0042 67 #define CONTROL_PADCONF_SDRC_D10 0x0044 68 #define CONTROL_PADCONF_SDRC_D11 0x0046 69 #define CONTROL_PADCONF_SDRC_D12 0x0048 70 #define CONTROL_PADCONF_SDRC_D13 0x004A 71 #define CONTROL_PADCONF_SDRC_D14 0x004C 72 #define CONTROL_PADCONF_SDRC_D15 0x004E 73 #define CONTROL_PADCONF_SDRC_D16 0x0050 74 #define CONTROL_PADCONF_SDRC_D17 0x0052 75 #define CONTROL_PADCONF_SDRC_D18 0x0054 76 #define CONTROL_PADCONF_SDRC_D19 0x0056 77 #define CONTROL_PADCONF_SDRC_D20 0x0058 78 #define CONTROL_PADCONF_SDRC_D21 0x005A 79 #define CONTROL_PADCONF_SDRC_D22 0x005C 80 #define CONTROL_PADCONF_SDRC_D23 0x005E 81 #define CONTROL_PADCONF_SDRC_D24 0x0060 82 #define CONTROL_PADCONF_SDRC_D25 0x0062 83 #define CONTROL_PADCONF_SDRC_D26 0x0064 84 #define CONTROL_PADCONF_SDRC_D27 0x0066 85 #define CONTROL_PADCONF_SDRC_D28 0x0068 86 #define CONTROL_PADCONF_SDRC_D29 0x006A 87 #define CONTROL_PADCONF_SDRC_D30 0x006C 88 #define CONTROL_PADCONF_SDRC_D31 0x006E 89 #define CONTROL_PADCONF_SDRC_CLK 0x0070 90 #define CONTROL_PADCONF_SDRC_DQS0 0x0072 91 #define CONTROL_PADCONF_SDRC_DQS1 0x0074 92 #define CONTROL_PADCONF_SDRC_DQS2 0x0076 93 #define CONTROL_PADCONF_SDRC_DQS3 0x0078 94 /*GPMC*/ 95 #define CONTROL_PADCONF_GPMC_A1 0x007A 96 #define CONTROL_PADCONF_GPMC_A2 0x007C 97 #define CONTROL_PADCONF_GPMC_A3 0x007E 98 #define CONTROL_PADCONF_GPMC_A4 0x0080 99 #define CONTROL_PADCONF_GPMC_A5 0x0082 100 #define CONTROL_PADCONF_GPMC_A6 0x0084 101 #define CONTROL_PADCONF_GPMC_A7 0x0086 102 #define CONTROL_PADCONF_GPMC_A8 0x0088 103 #define CONTROL_PADCONF_GPMC_A9 0x008A 104 #define CONTROL_PADCONF_GPMC_A10 0x008C 105 #define CONTROL_PADCONF_GPMC_D0 0x008E 106 #define CONTROL_PADCONF_GPMC_D1 0x0090 107 #define CONTROL_PADCONF_GPMC_D2 0x0092 108 #define CONTROL_PADCONF_GPMC_D3 0x0094 109 #define CONTROL_PADCONF_GPMC_D4 0x0096 110 #define CONTROL_PADCONF_GPMC_D5 0x0098 111 #define CONTROL_PADCONF_GPMC_D6 0x009A 112 #define CONTROL_PADCONF_GPMC_D7 0x009C 113 #define CONTROL_PADCONF_GPMC_D8 0x009E 114 #define CONTROL_PADCONF_GPMC_D9 0x00A0 115 #define CONTROL_PADCONF_GPMC_D10 0x00A2 116 #define CONTROL_PADCONF_GPMC_D11 0x00A4 117 #define CONTROL_PADCONF_GPMC_D12 0x00A6 118 #define CONTROL_PADCONF_GPMC_D13 0x00A8 119 #define CONTROL_PADCONF_GPMC_D14 0x00AA 120 #define CONTROL_PADCONF_GPMC_D15 0x00AC 121 #define CONTROL_PADCONF_GPMC_NCS0 0x00AE 122 #define CONTROL_PADCONF_GPMC_NCS1 0x00B0 123 #define CONTROL_PADCONF_GPMC_NCS2 0x00B2 124 #define CONTROL_PADCONF_GPMC_NCS3 0x00B4 125 #define CONTROL_PADCONF_GPMC_NCS4 0x00B6 126 #define CONTROL_PADCONF_GPMC_NCS5 0x00B8 127 #define CONTROL_PADCONF_GPMC_NCS6 0x00BA 128 #define CONTROL_PADCONF_GPMC_NCS7 0x00BC 129 #define CONTROL_PADCONF_GPMC_CLK 0x00BE 130 #define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 131 #define CONTROL_PADCONF_GPMC_NOE 0x00C2 132 #define CONTROL_PADCONF_GPMC_NWE 0x00C4 133 #define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 134 #define CONTROL_PADCONF_GPMC_NBE1 0x00C8 135 #define CONTROL_PADCONF_GPMC_NWP 0x00CA 136 #define CONTROL_PADCONF_GPMC_WAIT0 0x00CC 137 #define CONTROL_PADCONF_GPMC_WAIT1 0x00CE 138 #define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 139 #define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 140 /*DSS*/ 141 #define CONTROL_PADCONF_DSS_PCLK 0x00D4 142 #define CONTROL_PADCONF_DSS_HSYNC 0x00D6 143 #define CONTROL_PADCONF_DSS_VSYNC 0x00D8 144 #define CONTROL_PADCONF_DSS_ACBIAS 0x00DA 145 #define CONTROL_PADCONF_DSS_DATA0 0x00DC 146 #define CONTROL_PADCONF_DSS_DATA1 0x00DE 147 #define CONTROL_PADCONF_DSS_DATA2 0x00E0 148 #define CONTROL_PADCONF_DSS_DATA3 0x00E2 149 #define CONTROL_PADCONF_DSS_DATA4 0x00E4 150 #define CONTROL_PADCONF_DSS_DATA5 0x00E6 151 #define CONTROL_PADCONF_DSS_DATA6 0x00E8 152 #define CONTROL_PADCONF_DSS_DATA7 0x00EA 153 #define CONTROL_PADCONF_DSS_DATA8 0x00EC 154 #define CONTROL_PADCONF_DSS_DATA9 0x00EE 155 #define CONTROL_PADCONF_DSS_DATA10 0x00F0 156 #define CONTROL_PADCONF_DSS_DATA11 0x00F2 157 #define CONTROL_PADCONF_DSS_DATA12 0x00F4 158 #define CONTROL_PADCONF_DSS_DATA13 0x00F6 159 #define CONTROL_PADCONF_DSS_DATA14 0x00F8 160 #define CONTROL_PADCONF_DSS_DATA15 0x00FA 161 #define CONTROL_PADCONF_DSS_DATA16 0x00FC 162 #define CONTROL_PADCONF_DSS_DATA17 0x00FE 163 #define CONTROL_PADCONF_DSS_DATA18 0x0100 164 #define CONTROL_PADCONF_DSS_DATA19 0x0102 165 #define CONTROL_PADCONF_DSS_DATA20 0x0104 166 #define CONTROL_PADCONF_DSS_DATA21 0x0106 167 #define CONTROL_PADCONF_DSS_DATA22 0x0108 168 #define CONTROL_PADCONF_DSS_DATA23 0x010A 169 /*CAMERA*/ 170 #define CONTROL_PADCONF_CAM_HS 0x010C 171 #define CONTROL_PADCONF_CAM_VS 0x010E 172 #define CONTROL_PADCONF_CAM_XCLKA 0x0110 173 #define CONTROL_PADCONF_CAM_PCLK 0x0112 174 #define CONTROL_PADCONF_CAM_FLD 0x0114 175 #define CONTROL_PADCONF_CAM_D0 0x0116 176 #define CONTROL_PADCONF_CAM_D1 0x0118 177 #define CONTROL_PADCONF_CAM_D2 0x011A 178 #define CONTROL_PADCONF_CAM_D3 0x011C 179 #define CONTROL_PADCONF_CAM_D4 0x011E 180 #define CONTROL_PADCONF_CAM_D5 0x0120 181 #define CONTROL_PADCONF_CAM_D6 0x0122 182 #define CONTROL_PADCONF_CAM_D7 0x0124 183 #define CONTROL_PADCONF_CAM_D8 0x0126 184 #define CONTROL_PADCONF_CAM_D9 0x0128 185 #define CONTROL_PADCONF_CAM_D10 0x012A 186 #define CONTROL_PADCONF_CAM_D11 0x012C 187 #define CONTROL_PADCONF_CAM_XCLKB 0x012E 188 #define CONTROL_PADCONF_CAM_WEN 0x0130 189 #define CONTROL_PADCONF_CAM_STROBE 0x0132 190 #define CONTROL_PADCONF_CSI2_DX0 0x0134 191 #define CONTROL_PADCONF_CSI2_DY0 0x0136 192 #define CONTROL_PADCONF_CSI2_DX1 0x0138 193 #define CONTROL_PADCONF_CSI2_DY1 0x013A 194 /*Audio Interface */ 195 #define CONTROL_PADCONF_MCBSP2_FSX 0x013C 196 #define CONTROL_PADCONF_MCBSP2_CLKX 0x013E 197 #define CONTROL_PADCONF_MCBSP2_DR 0x0140 198 #define CONTROL_PADCONF_MCBSP2_DX 0x0142 199 #define CONTROL_PADCONF_MMC1_CLK 0x0144 200 #define CONTROL_PADCONF_MMC1_CMD 0x0146 201 #define CONTROL_PADCONF_MMC1_DAT0 0x0148 202 #define CONTROL_PADCONF_MMC1_DAT1 0x014A 203 #define CONTROL_PADCONF_MMC1_DAT2 0x014C 204 #define CONTROL_PADCONF_MMC1_DAT3 0x014E 205 #define CONTROL_PADCONF_MMC1_DAT4 0x0150 206 #define CONTROL_PADCONF_MMC1_DAT5 0x0152 207 #define CONTROL_PADCONF_MMC1_DAT6 0x0154 208 #define CONTROL_PADCONF_MMC1_DAT7 0x0156 209 /*Wireless LAN */ 210 #define CONTROL_PADCONF_MMC2_CLK 0x0158 211 #define CONTROL_PADCONF_MMC2_CMD 0x015A 212 #define CONTROL_PADCONF_MMC2_DAT0 0x015C 213 #define CONTROL_PADCONF_MMC2_DAT1 0x015E 214 #define CONTROL_PADCONF_MMC2_DAT2 0x0160 215 #define CONTROL_PADCONF_MMC2_DAT3 0x0162 216 #define CONTROL_PADCONF_MMC2_DAT4 0x0164 217 #define CONTROL_PADCONF_MMC2_DAT5 0x0166 218 #define CONTROL_PADCONF_MMC2_DAT6 0x0168 219 #define CONTROL_PADCONF_MMC2_DAT7 0x016A 220 /*Bluetooth*/ 221 #define CONTROL_PADCONF_MCBSP3_DX 0x016C 222 #define CONTROL_PADCONF_MCBSP3_DR 0x016E 223 #define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 224 #define CONTROL_PADCONF_MCBSP3_FSX 0x0172 225 #define CONTROL_PADCONF_UART2_CTS 0x0174 226 #define CONTROL_PADCONF_UART2_RTS 0x0176 227 #define CONTROL_PADCONF_UART2_TX 0x0178 228 #define CONTROL_PADCONF_UART2_RX 0x017A 229 /*Modem Interface */ 230 #define CONTROL_PADCONF_UART1_TX 0x017C 231 #define CONTROL_PADCONF_UART1_RTS 0x017E 232 #define CONTROL_PADCONF_UART1_CTS 0x0180 233 #define CONTROL_PADCONF_UART1_RX 0x0182 234 #define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 235 #define CONTROL_PADCONF_MCBSP4_DR 0x0186 236 #define CONTROL_PADCONF_MCBSP4_DX 0x0188 237 #define CONTROL_PADCONF_MCBSP4_FSX 0x018A 238 #define CONTROL_PADCONF_MCBSP1_CLKR 0x018C 239 #define CONTROL_PADCONF_MCBSP1_FSR 0x018E 240 #define CONTROL_PADCONF_MCBSP1_DX 0x0190 241 #define CONTROL_PADCONF_MCBSP1_DR 0x0192 242 #define CONTROL_PADCONF_MCBSP_CLKS 0x0194 243 #define CONTROL_PADCONF_MCBSP1_FSX 0x0196 244 #define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 245 /*Serial Interface*/ 246 #define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A 247 #define CONTROL_PADCONF_UART3_RTS_SD 0x019C 248 #define CONTROL_PADCONF_UART3_RX_IRRX 0x019E 249 #define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 250 #define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 251 #define CONTROL_PADCONF_HSUSB0_STP 0x01A4 252 #define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 253 #define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 254 #define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA 255 #define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC 256 #define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE 257 #define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 258 #define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 259 #define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 260 #define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 261 #define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 262 #define CONTROL_PADCONF_I2C1_SCL 0x01BA 263 #define CONTROL_PADCONF_I2C1_SDA 0x01BC 264 #define CONTROL_PADCONF_I2C2_SCL 0x01BE 265 #define CONTROL_PADCONF_I2C2_SDA 0x01C0 266 #define CONTROL_PADCONF_I2C3_SCL 0x01C2 267 #define CONTROL_PADCONF_I2C3_SDA 0x01C4 268 #define CONTROL_PADCONF_I2C4_SCL 0x0A00 269 #define CONTROL_PADCONF_I2C4_SDA 0x0A02 270 #define CONTROL_PADCONF_HDQ_SIO 0x01C6 271 #define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 272 #define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA 273 #define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC 274 #define CONTROL_PADCONF_MCSPI1_CS0 0x01CE 275 #define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 276 #define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 277 #define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 278 #define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 279 #define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 280 #define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA 281 #define CONTROL_PADCONF_MCSPI2_CS0 0x01DC 282 #define CONTROL_PADCONF_MCSPI2_CS1 0x01DE 283 /*Control and debug */ 284 #define CONTROL_PADCONF_SYS_32K 0x0A04 285 #define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 286 #define CONTROL_PADCONF_SYS_NIRQ 0x01E0 287 #define CONTROL_PADCONF_SYS_BOOT0 0x0A0A 288 #define CONTROL_PADCONF_SYS_BOOT1 0x0A0C 289 #define CONTROL_PADCONF_SYS_BOOT2 0x0A0E 290 #define CONTROL_PADCONF_SYS_BOOT3 0x0A10 291 #define CONTROL_PADCONF_SYS_BOOT4 0x0A12 292 #define CONTROL_PADCONF_SYS_BOOT5 0x0A14 293 #define CONTROL_PADCONF_SYS_BOOT6 0x0A16 294 #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 295 #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A 296 #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 297 #define CONTROL_PADCONF_JTAG_nTRST 0x0A1C 298 #define CONTROL_PADCONF_JTAG_TCK 0x0A1E 299 #define CONTROL_PADCONF_JTAG_TMS 0x0A20 300 #define CONTROL_PADCONF_JTAG_TDI 0x0A22 301 #define CONTROL_PADCONF_JTAG_EMU0 0x0A24 302 #define CONTROL_PADCONF_JTAG_EMU1 0x0A26 303 #define CONTROL_PADCONF_ETK_CLK 0x0A28 304 #define CONTROL_PADCONF_ETK_CTL 0x0A2A 305 #define CONTROL_PADCONF_ETK_D0 0x0A2C 306 #define CONTROL_PADCONF_ETK_D1 0x0A2E 307 #define CONTROL_PADCONF_ETK_D2 0x0A30 308 #define CONTROL_PADCONF_ETK_D3 0x0A32 309 #define CONTROL_PADCONF_ETK_D4 0x0A34 310 #define CONTROL_PADCONF_ETK_D5 0x0A36 311 #define CONTROL_PADCONF_ETK_D6 0x0A38 312 #define CONTROL_PADCONF_ETK_D7 0x0A3A 313 #define CONTROL_PADCONF_ETK_D8 0x0A3C 314 #define CONTROL_PADCONF_ETK_D9 0x0A3E 315 #define CONTROL_PADCONF_ETK_D10 0x0A40 316 #define CONTROL_PADCONF_ETK_D11 0x0A42 317 #define CONTROL_PADCONF_ETK_D12 0x0A44 318 #define CONTROL_PADCONF_ETK_D13 0x0A46 319 #define CONTROL_PADCONF_ETK_D14 0x0A48 320 #define CONTROL_PADCONF_ETK_D15 0x0A4A 321 #define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 322 #define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA 323 #define CONTROL_PADCONF_ETK_D0_ES2 0x05DC 324 #define CONTROL_PADCONF_ETK_D1_ES2 0x05DE 325 #define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 326 #define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 327 #define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 328 #define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 329 #define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 330 #define CONTROL_PADCONF_ETK_D7_ES2 0x05EA 331 #define CONTROL_PADCONF_ETK_D8_ES2 0x05EC 332 #define CONTROL_PADCONF_ETK_D9_ES2 0x05EE 333 #define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 334 #define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 335 #define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 336 #define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 337 #define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 338 #define CONTROL_PADCONF_ETK_D15_ES2 0x05FA 339 /*Die to Die */ 340 #define CONTROL_PADCONF_D2D_MCAD0 0x01E4 341 #define CONTROL_PADCONF_D2D_MCAD1 0x01E6 342 #define CONTROL_PADCONF_D2D_MCAD2 0x01E8 343 #define CONTROL_PADCONF_D2D_MCAD3 0x01EA 344 #define CONTROL_PADCONF_D2D_MCAD4 0x01EC 345 #define CONTROL_PADCONF_D2D_MCAD5 0x01EE 346 #define CONTROL_PADCONF_D2D_MCAD6 0x01F0 347 #define CONTROL_PADCONF_D2D_MCAD7 0x01F2 348 #define CONTROL_PADCONF_D2D_MCAD8 0x01F4 349 #define CONTROL_PADCONF_D2D_MCAD9 0x01F6 350 #define CONTROL_PADCONF_D2D_MCAD10 0x01F8 351 #define CONTROL_PADCONF_D2D_MCAD11 0x01FA 352 #define CONTROL_PADCONF_D2D_MCAD12 0x01FC 353 #define CONTROL_PADCONF_D2D_MCAD13 0x01FE 354 #define CONTROL_PADCONF_D2D_MCAD14 0x0200 355 #define CONTROL_PADCONF_D2D_MCAD15 0x0202 356 #define CONTROL_PADCONF_D2D_MCAD16 0x0204 357 #define CONTROL_PADCONF_D2D_MCAD17 0x0206 358 #define CONTROL_PADCONF_D2D_MCAD18 0x0208 359 #define CONTROL_PADCONF_D2D_MCAD19 0x020A 360 #define CONTROL_PADCONF_D2D_MCAD20 0x020C 361 #define CONTROL_PADCONF_D2D_MCAD21 0x020E 362 #define CONTROL_PADCONF_D2D_MCAD22 0x0210 363 #define CONTROL_PADCONF_D2D_MCAD23 0x0212 364 #define CONTROL_PADCONF_D2D_MCAD24 0x0214 365 #define CONTROL_PADCONF_D2D_MCAD25 0x0216 366 #define CONTROL_PADCONF_D2D_MCAD26 0x0218 367 #define CONTROL_PADCONF_D2D_MCAD27 0x021A 368 #define CONTROL_PADCONF_D2D_MCAD28 0x021C 369 #define CONTROL_PADCONF_D2D_MCAD29 0x021E 370 #define CONTROL_PADCONF_D2D_MCAD30 0x0220 371 #define CONTROL_PADCONF_D2D_MCAD31 0x0222 372 #define CONTROL_PADCONF_D2D_MCAD32 0x0224 373 #define CONTROL_PADCONF_D2D_MCAD33 0x0226 374 #define CONTROL_PADCONF_D2D_MCAD34 0x0228 375 #define CONTROL_PADCONF_D2D_MCAD35 0x022A 376 #define CONTROL_PADCONF_D2D_MCAD36 0x022C 377 #define CONTROL_PADCONF_D2D_CLK26MI 0x022E 378 #define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 379 #define CONTROL_PADCONF_D2D_NRESWARM 0x0232 380 #define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 381 #define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 382 #define CONTROL_PADCONF_D2D_SPINT 0x0238 383 #define CONTROL_PADCONF_D2D_FRINT 0x023A 384 #define CONTROL_PADCONF_D2D_DMAREQ0 0x023C 385 #define CONTROL_PADCONF_D2D_DMAREQ1 0x023E 386 #define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 387 #define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 388 #define CONTROL_PADCONF_D2D_N3GTRST 0x0244 389 #define CONTROL_PADCONF_D2D_N3GTDI 0x0246 390 #define CONTROL_PADCONF_D2D_N3GTDO 0x0248 391 #define CONTROL_PADCONF_D2D_N3GTMS 0x024A 392 #define CONTROL_PADCONF_D2D_N3GTCK 0x024C 393 #define CONTROL_PADCONF_D2D_N3GRTCK 0x024E 394 #define CONTROL_PADCONF_D2D_MSTDBY 0x0250 395 #define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C 396 #define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 397 #define CONTROL_PADCONF_D2D_IDLEACK 0x0254 398 #define CONTROL_PADCONF_D2D_MWRITE 0x0256 399 #define CONTROL_PADCONF_D2D_SWRITE 0x0258 400 #define CONTROL_PADCONF_D2D_MREAD 0x025A 401 #define CONTROL_PADCONF_D2D_SREAD 0x025C 402 #define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E 403 #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 404 #define CONTROL_PADCONF_SDRC_CKE0 0x0262 405 #define CONTROL_PADCONF_SDRC_CKE1 0x0264 406 407 #define MUX_VAL(OFFSET,VALUE)\ 408 writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); 409 410 #define CP(x) (CONTROL_PADCONF_##x) 411 412 #endif 413