1 /* 2 * (C) Copyright 2008 3 * Texas Instruments, <www.ti.com> 4 * Syed Mohammed Khasim <khasim@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation's version 2 of 12 * the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef MMC_HOST_DEF_H 26 #define MMC_HOST_DEF_H 27 28 /* T2 Register definitions */ 29 #define T2_BASE 0x48002000 30 31 typedef struct t2 { 32 unsigned char res1[0x274]; /* 0x000 */ 33 unsigned int devconf0; /* 0x274 */ 34 unsigned char res2[0x060]; /* 0x278 */ 35 unsigned int devconf1; /* 0x2D8 */ 36 unsigned char res3[0x244]; /* 0x2DC */ 37 unsigned int pbias_lite; /* 0x520 */ 38 } t2_t; 39 40 #define MMCSDIO1ADPCLKISEL (1 << 24) 41 #define MMCSDIO2ADPCLKISEL (1 << 6) 42 43 #define EN_MMC1 (1 << 24) 44 #define EN_MMC2 (1 << 25) 45 #define EN_MMC3 (1 << 30) 46 47 #define PBIASLITEPWRDNZ0 (1 << 1) 48 #define PBIASSPEEDCTRL0 (1 << 2) 49 #define PBIASLITEPWRDNZ1 (1 << 9) 50 51 /* 52 * OMAP HSMMC register definitions 53 */ 54 #define OMAP_HSMMC1_BASE 0x4809C000 55 #define OMAP_HSMMC2_BASE 0x480B4000 56 #define OMAP_HSMMC3_BASE 0x480AD000 57 58 typedef struct hsmmc { 59 unsigned char res1[0x10]; 60 unsigned int sysconfig; /* 0x10 */ 61 unsigned int sysstatus; /* 0x14 */ 62 unsigned char res2[0x14]; 63 unsigned int con; /* 0x2C */ 64 unsigned char res3[0xD4]; 65 unsigned int blk; /* 0x104 */ 66 unsigned int arg; /* 0x108 */ 67 unsigned int cmd; /* 0x10C */ 68 unsigned int rsp10; /* 0x110 */ 69 unsigned int rsp32; /* 0x114 */ 70 unsigned int rsp54; /* 0x118 */ 71 unsigned int rsp76; /* 0x11C */ 72 unsigned int data; /* 0x120 */ 73 unsigned int pstate; /* 0x124 */ 74 unsigned int hctl; /* 0x128 */ 75 unsigned int sysctl; /* 0x12C */ 76 unsigned int stat; /* 0x130 */ 77 unsigned int ie; /* 0x134 */ 78 unsigned char res4[0x8]; 79 unsigned int capa; /* 0x140 */ 80 } hsmmc_t; 81 82 /* 83 * OMAP HS MMC Bit definitions 84 */ 85 #define MMC_SOFTRESET (0x1 << 1) 86 #define RESETDONE (0x1 << 0) 87 #define NOOPENDRAIN (0x0 << 0) 88 #define OPENDRAIN (0x1 << 0) 89 #define OD (0x1 << 0) 90 #define INIT_NOINIT (0x0 << 1) 91 #define INIT_INITSTREAM (0x1 << 1) 92 #define HR_NOHOSTRESP (0x0 << 2) 93 #define STR_BLOCK (0x0 << 3) 94 #define MODE_FUNC (0x0 << 4) 95 #define DW8_1_4BITMODE (0x0 << 5) 96 #define MIT_CTO (0x0 << 6) 97 #define CDP_ACTIVEHIGH (0x0 << 7) 98 #define WPP_ACTIVEHIGH (0x0 << 8) 99 #define RESERVED_MASK (0x3 << 9) 100 #define CTPL_MMC_SD (0x0 << 11) 101 #define BLEN_512BYTESLEN (0x200 << 0) 102 #define NBLK_STPCNT (0x0 << 16) 103 #define DE_DISABLE (0x0 << 0) 104 #define BCE_DISABLE (0x0 << 1) 105 #define ACEN_DISABLE (0x0 << 2) 106 #define DDIR_OFFSET (4) 107 #define DDIR_MASK (0x1 << 4) 108 #define DDIR_WRITE (0x0 << 4) 109 #define DDIR_READ (0x1 << 4) 110 #define MSBS_SGLEBLK (0x0 << 5) 111 #define RSP_TYPE_OFFSET (16) 112 #define RSP_TYPE_MASK (0x3 << 16) 113 #define RSP_TYPE_NORSP (0x0 << 16) 114 #define RSP_TYPE_LGHT136 (0x1 << 16) 115 #define RSP_TYPE_LGHT48 (0x2 << 16) 116 #define RSP_TYPE_LGHT48B (0x3 << 16) 117 #define CCCE_NOCHECK (0x0 << 19) 118 #define CCCE_CHECK (0x1 << 19) 119 #define CICE_NOCHECK (0x0 << 20) 120 #define CICE_CHECK (0x1 << 20) 121 #define DP_OFFSET (21) 122 #define DP_MASK (0x1 << 21) 123 #define DP_NO_DATA (0x0 << 21) 124 #define DP_DATA (0x1 << 21) 125 #define CMD_TYPE_NORMAL (0x0 << 22) 126 #define INDEX_OFFSET (24) 127 #define INDEX_MASK (0x3f << 24) 128 #define INDEX(i) (i << 24) 129 #define DATI_MASK (0x1 << 1) 130 #define DATI_CMDDIS (0x1 << 1) 131 #define DTW_1_BITMODE (0x0 << 1) 132 #define DTW_4_BITMODE (0x1 << 1) 133 #define SDBP_PWROFF (0x0 << 8) 134 #define SDBP_PWRON (0x1 << 8) 135 #define SDVS_1V8 (0x5 << 9) 136 #define SDVS_3V0 (0x6 << 9) 137 #define ICE_MASK (0x1 << 0) 138 #define ICE_STOP (0x0 << 0) 139 #define ICS_MASK (0x1 << 1) 140 #define ICS_NOTREADY (0x0 << 1) 141 #define ICE_OSCILLATE (0x1 << 0) 142 #define CEN_MASK (0x1 << 2) 143 #define CEN_DISABLE (0x0 << 2) 144 #define CEN_ENABLE (0x1 << 2) 145 #define CLKD_OFFSET (6) 146 #define CLKD_MASK (0x3FF << 6) 147 #define DTO_MASK (0xF << 16) 148 #define DTO_15THDTO (0xE << 16) 149 #define SOFTRESETALL (0x1 << 24) 150 #define CC_MASK (0x1 << 0) 151 #define TC_MASK (0x1 << 1) 152 #define BWR_MASK (0x1 << 4) 153 #define BRR_MASK (0x1 << 5) 154 #define ERRI_MASK (0x1 << 15) 155 #define IE_CC (0x01 << 0) 156 #define IE_TC (0x01 << 1) 157 #define IE_BWR (0x01 << 4) 158 #define IE_BRR (0x01 << 5) 159 #define IE_CTO (0x01 << 16) 160 #define IE_CCRC (0x01 << 17) 161 #define IE_CEB (0x01 << 18) 162 #define IE_CIE (0x01 << 19) 163 #define IE_DTO (0x01 << 20) 164 #define IE_DCRC (0x01 << 21) 165 #define IE_DEB (0x01 << 22) 166 #define IE_CERR (0x01 << 28) 167 #define IE_BADA (0x01 << 29) 168 169 #define VS30_3V0SUP (1 << 25) 170 #define VS18_1V8SUP (1 << 26) 171 172 /* Driver definitions */ 173 #define MMCSD_SECTOR_SIZE 512 174 #define MMC_CARD 0 175 #define SD_CARD 1 176 #define BYTE_MODE 0 177 #define SECTOR_MODE 1 178 #define CLK_INITSEQ 0 179 #define CLK_400KHZ 1 180 #define CLK_MISC 2 181 182 typedef struct { 183 unsigned int card_type; 184 unsigned int version; 185 unsigned int mode; 186 unsigned int size; 187 unsigned int RCA; 188 } mmc_card_data; 189 190 #define mmc_reg_out(addr, mask, val)\ 191 writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) 192 193 #endif /* MMC_HOST_DEF_H */ 194