1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* 43 * For a full explanation of these registers and values please see 44 * the Technical Reference Manual (TRM) for any of the processors in 45 * this family. 46 */ 47 48 /* Slower full frequency range default timings for x32 operation*/ 49 #define SDRC_SHARING 0x00000100 50 #define SDRC_MR_0_SDR 0x00000031 51 52 /* 53 * SDRC autorefresh control values. This register consists of autorefresh 54 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The 55 * counter is a result of ( tREFI / tCK ) - 50. 56 */ 57 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 58 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ 59 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ 60 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ 61 62 #define DLL_OFFSET 0 63 #define DLL_WRITEDDRCLKX2DIS 1 64 #define DLL_ENADLL 1 65 #define DLL_LOCKDLL 0 66 #define DLL_DLLPHASE_72 0 67 #define DLL_DLLPHASE_90 1 68 69 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 70 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 71 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 72 73 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 74 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 75 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 76 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 77 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 78 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 79 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 80 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 81 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 82 83 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ 84 ACTIM_CTRLA_TRFC(a) | \ 85 ACTIM_CTRLA_TRC(b) | \ 86 ACTIM_CTRLA_TRAS(b) | \ 87 ACTIM_CTRLA_TRP(d) | \ 88 ACTIM_CTRLA_TRCD(e) | \ 89 ACTIM_CTRLA_TRRD(f) | \ 90 ACTIM_CTRLA_TDPL(g) | \ 91 ACTIM_CTRLA_TDAL(h) 92 93 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 94 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 95 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 96 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 97 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 98 99 #define ACTIM_CTRLB(a,b,c,d) \ 100 ACTIM_CTRLB_TWTR(a) | \ 101 ACTIM_CTRLB_TCKE(b) | \ 102 ACTIM_CTRLB_TXP(b) | \ 103 ACTIM_CTRLB_TXSR(d) 104 105 /* 106 * Values used in the MCFG register. Only values we use today 107 * are defined and the rest can be found in the TRM. Unless otherwise 108 * noted all fields are one bit. 109 */ 110 #define V_MCFG_RAMTYPE_DDR (0x1) 111 #define V_MCFG_DEEPPD_EN (0x1 << 3) 112 #define V_MCFG_B32NOT16_32 (0x1 << 4) 113 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ 114 #define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ 115 #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) 116 #define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ 117 #define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ 118 119 /* Macro to construct MCFG */ 120 #define MCFG(a, b) \ 121 V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ 122 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ 123 V_MCFG_BANKALLOCATION_RBC | \ 124 V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR 125 126 /* Hynix part of Overo (165MHz optimized) 6.06ns */ 127 #define HYNIX_TDAL_165 6 128 #define HYNIX_TDPL_165 3 129 #define HYNIX_TRRD_165 2 130 #define HYNIX_TRCD_165 3 131 #define HYNIX_TRP_165 3 132 #define HYNIX_TRAS_165 7 133 #define HYNIX_TRC_165 10 134 #define HYNIX_TRFC_165 21 135 #define HYNIX_V_ACTIMA_165 \ 136 ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ 137 HYNIX_TRAS_165, HYNIX_TRP_165, \ 138 HYNIX_TRCD_165, HYNIX_TRRD_165, \ 139 HYNIX_TDPL_165, HYNIX_TDAL_165) 140 141 #define HYNIX_TWTR_165 1 142 #define HYNIX_TCKE_165 1 143 #define HYNIX_TXP_165 2 144 #define HYNIX_XSR_165 24 145 #define HYNIX_V_ACTIMB_165 \ 146 ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ 147 HYNIX_TXP_165, HYNIX_XSR_165) 148 149 #define HYNIX_RASWIDTH_165 0x2 150 #define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) 151 152 /* Hynix part of AM/DM37xEVM (200MHz optimized) */ 153 #define HYNIX_TDAL_200 6 154 #define HYNIX_TDPL_200 3 155 #define HYNIX_TRRD_200 2 156 #define HYNIX_TRCD_200 4 157 #define HYNIX_TRP_200 3 158 #define HYNIX_TRAS_200 8 159 #define HYNIX_TRC_200 11 160 #define HYNIX_TRFC_200 18 161 #define HYNIX_V_ACTIMA_200 \ 162 ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ 163 HYNIX_TRAS_200, HYNIX_TRP_200, \ 164 HYNIX_TRCD_200, HYNIX_TRRD_200, \ 165 HYNIX_TDPL_200, HYNIX_TDAL_200) 166 167 #define HYNIX_TWTR_200 2 168 #define HYNIX_TCKE_200 1 169 #define HYNIX_TXP_200 1 170 #define HYNIX_XSR_200 28 171 #define HYNIX_V_ACTIMB_200 \ 172 ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ 173 HYNIX_TXP_200, HYNIX_XSR_200) 174 175 #define HYNIX_RASWIDTH_200 0x3 176 #define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) 177 178 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 179 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 180 /* 15/6 + 18/6 = 5.5 -> 6 */ 181 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 182 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 183 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 184 #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 185 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 186 #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 187 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 188 189 #define INFINEON_V_ACTIMA_165 \ 190 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 191 INFINEON_TRAS_165, INFINEON_TRP_165, \ 192 INFINEON_TRCD_165, INFINEON_TRRD_165, \ 193 INFINEON_TDPL_165, INFINEON_TDAL_165) 194 195 #define INFINEON_TWTR_165 1 196 #define INFINEON_TCKE_165 2 197 #define INFINEON_TXP_165 2 198 #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 199 200 #define INFINEON_V_ACTIMB_165 \ 201 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 202 INFINEON_TXP_165, INFINEON_XSR_165) 203 204 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 205 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 206 /* 15/6 + 18/6 = 5.5 -> 6 */ 207 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 208 #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 209 #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 210 #define MICRON_TRP_165 3 /* 18/6 = 3 */ 211 #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 212 #define MICRON_TRC_165 10 /* 60/6 = 10 */ 213 #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 214 215 #define MICRON_V_ACTIMA_165 \ 216 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 217 MICRON_TRAS_165, MICRON_TRP_165, \ 218 MICRON_TRCD_165, MICRON_TRRD_165, \ 219 MICRON_TDPL_165, MICRON_TDAL_165) 220 221 #define MICRON_TWTR_165 1 222 #define MICRON_TCKE_165 1 223 #define MICRON_XSR_165 23 /* 138/6 = 23 */ 224 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 225 226 #define MICRON_V_ACTIMB_165 \ 227 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 228 MICRON_TXP_165, MICRON_XSR_165) 229 230 #define MICRON_RASWIDTH_165 0x2 231 #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) 232 233 #define MICRON_BL_165 0x2 234 #define MICRON_SIL_165 0x0 235 #define MICRON_CASL_165 0x3 236 #define MICRON_WBST_165 0x0 237 #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ 238 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ 239 (MICRON_BL_165)) 240 241 /* Micron part (200MHz optimized) 5 ns */ 242 #define MICRON_TDAL_200 6 243 #define MICRON_TDPL_200 3 244 #define MICRON_TRRD_200 2 245 #define MICRON_TRCD_200 3 246 #define MICRON_TRP_200 3 247 #define MICRON_TRAS_200 8 248 #define MICRON_TRC_200 11 249 #define MICRON_TRFC_200 15 250 #define MICRON_V_ACTIMA_200 \ 251 ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ 252 MICRON_TRAS_200, MICRON_TRP_200, \ 253 MICRON_TRCD_200, MICRON_TRRD_200, \ 254 MICRON_TDPL_200, MICRON_TDAL_200) 255 256 #define MICRON_TWTR_200 2 257 #define MICRON_TCKE_200 4 258 #define MICRON_TXP_200 2 259 #define MICRON_XSR_200 23 260 #define MICRON_V_ACTIMB_200 \ 261 ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ 262 MICRON_TXP_200, MICRON_XSR_200) 263 264 #define MICRON_RASWIDTH_200 0x3 265 #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) 266 267 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 268 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 269 /* 15/6 + 18/6 = 5.5 -> 6 */ 270 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 271 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 272 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 273 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 274 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 275 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 276 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 277 278 #define NUMONYX_V_ACTIMA_165 \ 279 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 280 NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 281 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 282 NUMONYX_TDPL_165, NUMONYX_TDAL_165) 283 284 #define NUMONYX_TWTR_165 2 285 #define NUMONYX_TCKE_165 2 286 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 287 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 288 289 #define NUMONYX_V_ACTIMB_165 \ 290 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 291 NUMONYX_TXP_165, NUMONYX_XSR_165) 292 293 #define NUMONYX_RASWIDTH_165 0x4 294 #define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) 295 296 /* 297 * GPMC settings - 298 * Definitions is as per the following format 299 * #define <PART>_GPMC_CONFIG<x> <value> 300 * Where: 301 * PART is the part name e.g. STNOR - Intel Strata Flash 302 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 303 * Value is corresponding value 304 * 305 * For every valid PRCM configuration there should be only one definition of 306 * the same. if values are independent of the board, this definition will be 307 * present in this file if values are dependent on the board, then this should 308 * go into corresponding mem-boardName.h file 309 * 310 * Currently valid part Names are (PART): 311 * STNOR - Intel Strata Flash 312 * SMNAND - Samsung NAND 313 * MPDB - H4 MPDB board 314 * SBNOR - Sibley NOR 315 * MNAND - Micron Large page x16 NAND 316 * ONNAND - Samsung One NAND 317 * 318 * include/configs/file.h contains the defn - for all CS we are interested 319 * #define OMAP34XX_GPMC_CSx PART 320 * #define OMAP34XX_GPMC_CSx_SIZE Size 321 * #define OMAP34XX_GPMC_CSx_MAP Map 322 * Where: 323 * x - CS number 324 * PART - Part Name as defined above 325 * SIZE - how big is the mapping to be 326 * GPMC_SIZE_128M - 0x8 327 * GPMC_SIZE_64M - 0xC 328 * GPMC_SIZE_32M - 0xE 329 * GPMC_SIZE_16M - 0xF 330 * MAP - Map this CS to which address(GPMC address space)- Absolute address 331 * >>24 before being used. 332 */ 333 #define GPMC_SIZE_128M 0x8 334 #define GPMC_SIZE_64M 0xC 335 #define GPMC_SIZE_32M 0xE 336 #define GPMC_SIZE_16M 0xF 337 338 #define GPMC_BASEADDR_MASK 0x3F 339 340 #define GPMC_CS_ENABLE 0x1 341 342 #define SMNAND_GPMC_CONFIG1 0x00000800 343 #define SMNAND_GPMC_CONFIG2 0x00141400 344 #define SMNAND_GPMC_CONFIG3 0x00141400 345 #define SMNAND_GPMC_CONFIG4 0x0F010F01 346 #define SMNAND_GPMC_CONFIG5 0x010C1414 347 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 348 #define SMNAND_GPMC_CONFIG7 0x00000C44 349 350 #define M_NAND_GPMC_CONFIG1 0x00001800 351 #define M_NAND_GPMC_CONFIG2 0x00141400 352 #define M_NAND_GPMC_CONFIG3 0x00141400 353 #define M_NAND_GPMC_CONFIG4 0x0F010F01 354 #define M_NAND_GPMC_CONFIG5 0x010C1414 355 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 356 #define M_NAND_GPMC_CONFIG7 0x00000C44 357 358 #define STNOR_GPMC_CONFIG1 0x3 359 #define STNOR_GPMC_CONFIG2 0x00151501 360 #define STNOR_GPMC_CONFIG3 0x00060602 361 #define STNOR_GPMC_CONFIG4 0x11091109 362 #define STNOR_GPMC_CONFIG5 0x01141F1F 363 #define STNOR_GPMC_CONFIG6 0x000004c4 364 365 #define SIBNOR_GPMC_CONFIG1 0x1200 366 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 367 #define SIBNOR_GPMC_CONFIG3 0x00080802 368 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 369 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 370 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 371 372 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 373 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 374 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 375 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 376 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 377 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 378 379 #define MPDB_GPMC_CONFIG1 0x00011000 380 #define MPDB_GPMC_CONFIG2 0x001f1f01 381 #define MPDB_GPMC_CONFIG3 0x00080803 382 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 383 #define MPDB_GPMC_CONFIG5 0x041f1F1F 384 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 385 386 #define P2_GPMC_CONFIG1 0x0 387 #define P2_GPMC_CONFIG2 0x0 388 #define P2_GPMC_CONFIG3 0x0 389 #define P2_GPMC_CONFIG4 0x0 390 #define P2_GPMC_CONFIG5 0x0 391 #define P2_GPMC_CONFIG6 0x0 392 393 #define ONENAND_GPMC_CONFIG1 0x00001200 394 #define ONENAND_GPMC_CONFIG2 0x000F0F01 395 #define ONENAND_GPMC_CONFIG3 0x00030301 396 #define ONENAND_GPMC_CONFIG4 0x0F040F04 397 #define ONENAND_GPMC_CONFIG5 0x010F1010 398 #define ONENAND_GPMC_CONFIG6 0x1F060000 399 400 #define NET_GPMC_CONFIG1 0x00001000 401 #define NET_GPMC_CONFIG2 0x001e1e01 402 #define NET_GPMC_CONFIG3 0x00080300 403 #define NET_GPMC_CONFIG4 0x1c091c09 404 #define NET_GPMC_CONFIG5 0x04181f1f 405 #define NET_GPMC_CONFIG6 0x00000FCF 406 #define NET_GPMC_CONFIG7 0x00000f6c 407 408 /* max number of GPMC Chip Selects */ 409 #define GPMC_MAX_CS 8 410 /* max number of GPMC regs */ 411 #define GPMC_MAX_REG 7 412 413 #define PISMO1_NOR 1 414 #define PISMO1_NAND 2 415 #define PISMO2_CS0 3 416 #define PISMO2_CS1 4 417 #define PISMO1_ONENAND 5 418 #define DBG_MPDB 6 419 #define PISMO2_NAND_CS0 7 420 #define PISMO2_NAND_CS1 8 421 422 /* make it readable for the gpmc_init */ 423 #define PISMO1_NOR_BASE FLASH_BASE 424 #define PISMO1_NAND_BASE NAND_BASE 425 #define PISMO2_CS0_BASE PISMO2_MAP1 426 #define PISMO1_ONEN_BASE ONENAND_MAP 427 #define DBG_MPDB_BASE DEBUG_BASE 428 429 #ifndef __ASSEMBLY__ 430 431 /* Function prototypes */ 432 void mem_init(void); 433 434 u32 is_mem_sdr(void); 435 u32 mem_ok(u32 cs); 436 437 u32 get_sdr_cs_size(u32); 438 u32 get_sdr_cs_offset(u32); 439 440 #endif /* __ASSEMBLY__ */ 441 442 #endif /* endif _MEM_H_ */ 443