1 /*
2  * (C) Copyright 2006-2008
3  * Texas Instruments, <www.ti.com>
4  * Richard Woodruff <r-woodruff2@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #ifndef _MEM_H_
26 #define _MEM_H_
27 
28 #define CS0		0x0
29 #define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
30 
31 #ifndef __ASSEMBLY__
32 enum {
33 	STACKED = 0,
34 	IP_DDR = 1,
35 	COMBO_DDR = 2,
36 	IP_SDR = 3,
37 };
38 #endif /* __ASSEMBLY__ */
39 
40 #define EARLY_INIT	1
41 
42 /*
43  * For a full explanation of these registers and values please see
44  * the Technical Reference Manual (TRM) for any of the processors in
45  * this family.
46  */
47 
48 /* Slower full frequency range default timings for x32 operation*/
49 #define SDRC_SHARING	0x00000100
50 #define SDRC_MR_0_SDR	0x00000031
51 
52 /*
53  * SDRC autorefresh control values.  This register consists of autorefresh
54  * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
55  * counter is a result of ( tREFI / tCK ) - 50.
56  */
57 #define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
58 #define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
59 #define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
60 #define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
61 
62 #define DLL_OFFSET		0
63 #define DLL_WRITEDDRCLKX2DIS	1
64 #define DLL_ENADLL		1
65 #define DLL_LOCKDLL		0
66 #define DLL_DLLPHASE_72		0
67 #define DLL_DLLPHASE_90		1
68 
69 /* rkw - need to find of 90/72 degree recommendation for speed like before */
70 #define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
71 				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
72 
73 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
74 #define ACTIM_CTRLA_TRFC(v)	(((v) & 0x1F) << 27)	/* 31:27 */
75 #define ACTIM_CTRLA_TRC(v)	(((v) & 0x1F) << 22)	/* 26:22 */
76 #define ACTIM_CTRLA_TRAS(v)	(((v) & 0x0F) << 18)	/* 21:18 */
77 #define ACTIM_CTRLA_TRP(v)	(((v) & 0x07) << 15)	/* 17:15 */
78 #define ACTIM_CTRLA_TRCD(v)	(((v) & 0x07) << 12)	/* 14:12 */
79 #define ACTIM_CTRLA_TRRD(v)	(((v) & 0x07) << 9)	/* 11:9  */
80 #define ACTIM_CTRLA_TDPL(v)	(((v) & 0x07) << 6)	/*  8:6  */
81 #define ACTIM_CTRLA_TDAL(v)	(v & 0x1F)		/*  4:0  */
82 
83 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal)	\
84 		ACTIM_CTRLA_TRFC(trfc)	|	\
85 		ACTIM_CTRLA_TRC(trc)	|	\
86 		ACTIM_CTRLA_TRAS(tras)	|	\
87 		ACTIM_CTRLA_TRP(trp)	|	\
88 		ACTIM_CTRLA_TRCD(trcd)	|	\
89 		ACTIM_CTRLA_TRRD(trrd)	|	\
90 		ACTIM_CTRLA_TDPL(tdpl)	|	\
91 		ACTIM_CTRLA_TDAL(tdal)
92 
93 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
94 #define ACTIM_CTRLB_TWTR(v)	(((v) & 0x03) << 16)	/* 17:16 */
95 #define ACTIM_CTRLB_TCKE(v)	(((v) & 0x07) << 12)	/* 14:12 */
96 #define ACTIM_CTRLB_TXP(v)	(((v) & 0x07) << 8)	/* 10:8  */
97 #define ACTIM_CTRLB_TXSR(v)	(v & 0xFF)		/*  7:0  */
98 
99 #define ACTIM_CTRLB(twtr, tcke, txp, txsr)		\
100 		ACTIM_CTRLB_TWTR(twtr)	|	\
101 		ACTIM_CTRLB_TCKE(tcke)	|	\
102 		ACTIM_CTRLB_TXP(txp)	|	\
103 		ACTIM_CTRLB_TXSR(txsr)
104 
105 /*
106  * Values used in the MCFG register.  Only values we use today
107  * are defined and the rest can be found in the TRM.  Unless otherwise
108  * noted all fields are one bit.
109  */
110 #define V_MCFG_RAMTYPE_DDR		(0x1)
111 #define V_MCFG_DEEPPD_EN		(0x1 << 3)
112 #define V_MCFG_B32NOT16_32		(0x1 << 4)
113 #define V_MCFG_BANKALLOCATION_RBC	(0x2 << 6)		/* 6:7 */
114 #define V_MCFG_RAMSIZE(ramsize)		((((ramsize) >> 20)/2) << 8) /* 8:17 */
115 #define V_MCFG_ADDRMUXLEGACY_FLEX	(0x1 << 19)
116 #define V_MCFG_CASWIDTH(caswidth)	(((caswidth)-5) << 20)	/* 20:22 */
117 #define V_MCFG_CASWIDTH_10B		V_MCFG_CASWIDTH(10)
118 #define V_MCFG_RASWIDTH(raswidth)	(((raswidth)-11) << 24)	/* 24:26 */
119 
120 /* Macro to construct MCFG */
121 #define MCFG(ramsize, raswidth)						\
122 		V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B |	\
123 		V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) |	\
124 		V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 |	\
125 		V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
126 
127 /* Hynix part of Overo (165MHz optimized) 6.06ns */
128 #define HYNIX_TDAL_165   6
129 #define HYNIX_TDPL_165   3
130 #define HYNIX_TRRD_165   2
131 #define HYNIX_TRCD_165   3
132 #define HYNIX_TRP_165    3
133 #define HYNIX_TRAS_165   7
134 #define HYNIX_TRC_165   10
135 #define HYNIX_TRFC_165  21
136 #define HYNIX_V_ACTIMA_165	\
137 		ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165,	\
138 				HYNIX_TRAS_165, HYNIX_TRP_165,	\
139 				HYNIX_TRCD_165, HYNIX_TRRD_165,	\
140 				HYNIX_TDPL_165, HYNIX_TDAL_165)
141 
142 #define HYNIX_TWTR_165   1
143 #define HYNIX_TCKE_165   1
144 #define HYNIX_TXP_165    2
145 #define HYNIX_XSR_165    24
146 #define HYNIX_V_ACTIMB_165	\
147 		ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165,	\
148 				HYNIX_TXP_165, HYNIX_XSR_165)
149 
150 #define HYNIX_RASWIDTH_165	13
151 #define HYNIX_V_MCFG_165(size)	MCFG((size), HYNIX_RASWIDTH_165)
152 
153 /* Hynix part of AM/DM37xEVM (200MHz optimized) */
154 #define HYNIX_TDAL_200		6
155 #define HYNIX_TDPL_200		3
156 #define HYNIX_TRRD_200		2
157 #define HYNIX_TRCD_200		4
158 #define HYNIX_TRP_200		3
159 #define HYNIX_TRAS_200		8
160 #define HYNIX_TRC_200		11
161 #define HYNIX_TRFC_200		18
162 #define HYNIX_V_ACTIMA_200	\
163 		ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200,	\
164 				HYNIX_TRAS_200, HYNIX_TRP_200,	\
165 				HYNIX_TRCD_200, HYNIX_TRRD_200,	\
166 				HYNIX_TDPL_200, HYNIX_TDAL_200)
167 
168 #define HYNIX_TWTR_200		2
169 #define HYNIX_TCKE_200		1
170 #define HYNIX_TXP_200		1
171 #define HYNIX_XSR_200		28
172 #define HYNIX_V_ACTIMB_200	\
173 		ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200,	\
174 				HYNIX_TXP_200, HYNIX_XSR_200)
175 
176 #define HYNIX_RASWIDTH_200	14
177 #define HYNIX_V_MCFG_200(size)	MCFG((size), HYNIX_RASWIDTH_200)
178 
179 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
180 #define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
181 					/* 15/6 + 18/6 = 5.5 -> 6	*/
182 #define INFINEON_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
183 #define INFINEON_TRRD_165	2	/* 12/6 = 2			*/
184 #define INFINEON_TRCD_165	3	/* 18/6 = 3			*/
185 #define INFINEON_TRP_165	3	/* 18/6 = 3			*/
186 #define INFINEON_TRAS_165	7	/* 42/6 = 7			*/
187 #define INFINEON_TRC_165	10	/* 60/6 = 10			*/
188 #define INFINEON_TRFC_165	12	/* 72/6 = 12			*/
189 
190 #define INFINEON_V_ACTIMA_165	\
191 		ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165,	\
192 				INFINEON_TRAS_165, INFINEON_TRP_165,	\
193 				INFINEON_TRCD_165, INFINEON_TRRD_165,	\
194 				INFINEON_TDPL_165, INFINEON_TDAL_165)
195 
196 #define INFINEON_TWTR_165	1
197 #define INFINEON_TCKE_165	2
198 #define INFINEON_TXP_165	2
199 #define INFINEON_XSR_165	20	/* 120/6 = 20	*/
200 
201 #define INFINEON_V_ACTIMB_165	\
202 		ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165,	\
203 				INFINEON_TXP_165, INFINEON_XSR_165)
204 
205 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
206 #define MICRON_TDAL_165		6	/* Twr/Tck + Trp/tck		*/
207 					/* 15/6 + 18/6 = 5.5 -> 6	*/
208 #define MICRON_TDPL_165		3	/* 15/6 = 2.5 -> 3 (Twr)	*/
209 #define MICRON_TRRD_165		2	/* 12/6 = 2			*/
210 #define MICRON_TRCD_165		3	/* 18/6 = 3			*/
211 #define MICRON_TRP_165		3	/* 18/6 = 3			*/
212 #define MICRON_TRAS_165		7	/* 42/6 = 7			*/
213 #define MICRON_TRC_165		10	/* 60/6 = 10			*/
214 #define MICRON_TRFC_165		21	/* 125/6 = 21			*/
215 
216 #define MICRON_V_ACTIMA_165	\
217 		ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165,		\
218 				MICRON_TRAS_165, MICRON_TRP_165,	\
219 				MICRON_TRCD_165, MICRON_TRRD_165,	\
220 				MICRON_TDPL_165, MICRON_TDAL_165)
221 
222 #define MICRON_TWTR_165		1
223 #define MICRON_TCKE_165		1
224 #define MICRON_XSR_165		23	/* 138/6 = 23		*/
225 #define MICRON_TXP_165		5	/* 25/6 = 4.1 => ~5	*/
226 
227 #define MICRON_V_ACTIMB_165	\
228 		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
229 				MICRON_TXP_165,	MICRON_XSR_165)
230 
231 #define MICRON_RASWIDTH_165	13
232 #define MICRON_V_MCFG_165(size)	MCFG((size), MICRON_RASWIDTH_165)
233 
234 #define MICRON_BL_165			0x2
235 #define MICRON_SIL_165			0x0
236 #define MICRON_CASL_165			0x3
237 #define MICRON_WBST_165			0x0
238 #define MICRON_V_MR_165			((MICRON_WBST_165 << 9) | \
239 		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
240 		(MICRON_BL_165))
241 
242 /* Micron part (200MHz optimized) 5 ns */
243 #define MICRON_TDAL_200		6
244 #define MICRON_TDPL_200		3
245 #define MICRON_TRRD_200		2
246 #define MICRON_TRCD_200		3
247 #define MICRON_TRP_200		3
248 #define MICRON_TRAS_200		8
249 #define MICRON_TRC_200		11
250 #define MICRON_TRFC_200		15
251 #define MICRON_V_ACTIMA_200	\
252 		ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200,		\
253 				MICRON_TRAS_200, MICRON_TRP_200,	\
254 				MICRON_TRCD_200, MICRON_TRRD_200,	\
255 				MICRON_TDPL_200, MICRON_TDAL_200)
256 
257 #define MICRON_TWTR_200		2
258 #define MICRON_TCKE_200		4
259 #define MICRON_TXP_200		2
260 #define MICRON_XSR_200		23
261 #define MICRON_V_ACTIMB_200	\
262 		ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200,	\
263 				MICRON_TXP_200,	MICRON_XSR_200)
264 
265 #define MICRON_RASWIDTH_200	14
266 #define MICRON_V_MCFG_200(size)	MCFG((size), MICRON_RASWIDTH_200)
267 
268 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
269 #define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
270 					/* 15/6 + 18/6 = 5.5 -> 6	*/
271 #define NUMONYX_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
272 #define NUMONYX_TRRD_165	2	/* 12/6 = 2			*/
273 #define NUMONYX_TRCD_165	4	/* 22.5/6 = 3.75 -> 4		*/
274 #define NUMONYX_TRP_165		3	/* 18/6 = 3			*/
275 #define NUMONYX_TRAS_165	7	/* 42/6 = 7			*/
276 #define NUMONYX_TRC_165		10	/* 60/6 = 10			*/
277 #define NUMONYX_TRFC_165	24	/* 140/6 = 23.3 -> 24		*/
278 
279 #define NUMONYX_V_ACTIMA_165	\
280 		ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165,		\
281 				NUMONYX_TRAS_165, NUMONYX_TRP_165,	\
282 				NUMONYX_TRCD_165, NUMONYX_TRRD_165,	\
283 				NUMONYX_TDPL_165, NUMONYX_TDAL_165)
284 
285 #define NUMONYX_TWTR_165	2
286 #define NUMONYX_TCKE_165	2
287 #define NUMONYX_TXP_165		3	/* 200/6 =  33.3 -> 34	*/
288 #define NUMONYX_XSR_165		34	/* 1.0 + 1.1 = 2.1 -> 3	*/
289 
290 #define NUMONYX_V_ACTIMB_165	\
291 		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
292 				NUMONYX_TXP_165, NUMONYX_XSR_165)
293 
294 #define NUMONYX_RASWIDTH_165		15
295 #define NUMONYX_V_MCFG_165(size)	MCFG((size), NUMONYX_RASWIDTH_165)
296 
297 /*
298  * GPMC settings -
299  * Definitions is as per the following format
300  * #define <PART>_GPMC_CONFIG<x> <value>
301  * Where:
302  * PART is the part name e.g. STNOR - Intel Strata Flash
303  * x is GPMC config registers from 1 to 6 (there will be 6 macros)
304  * Value is corresponding value
305  *
306  * For every valid PRCM configuration there should be only one definition of
307  * the same. if values are independent of the board, this definition will be
308  * present in this file if values are dependent on the board, then this should
309  * go into corresponding mem-boardName.h file
310  *
311  * Currently valid part Names are (PART):
312  * STNOR - Intel Strata Flash
313  * SMNAND - Samsung NAND
314  * MPDB - H4 MPDB board
315  * SBNOR - Sibley NOR
316  * MNAND - Micron Large page x16 NAND
317  * ONNAND - Samsung One NAND
318  *
319  * include/configs/file.h contains the defn - for all CS we are interested
320  * #define OMAP34XX_GPMC_CSx PART
321  * #define OMAP34XX_GPMC_CSx_SIZE Size
322  * #define OMAP34XX_GPMC_CSx_MAP Map
323  * Where:
324  * x - CS number
325  * PART - Part Name as defined above
326  * SIZE - how big is the mapping to be
327  *   GPMC_SIZE_128M - 0x8
328  *   GPMC_SIZE_64M  - 0xC
329  *   GPMC_SIZE_32M  - 0xE
330  *   GPMC_SIZE_16M  - 0xF
331  * MAP  - Map this CS to which address(GPMC address space)- Absolute address
332  *   >>24 before being used.
333  */
334 #define GPMC_SIZE_128M	0x8
335 #define GPMC_SIZE_64M	0xC
336 #define GPMC_SIZE_32M	0xE
337 #define GPMC_SIZE_16M	0xF
338 
339 #define GPMC_BASEADDR_MASK	0x3F
340 
341 #define GPMC_CS_ENABLE		0x1
342 
343 #define SMNAND_GPMC_CONFIG1	0x00000800
344 #define SMNAND_GPMC_CONFIG2	0x00141400
345 #define SMNAND_GPMC_CONFIG3	0x00141400
346 #define SMNAND_GPMC_CONFIG4	0x0F010F01
347 #define SMNAND_GPMC_CONFIG5	0x010C1414
348 #define SMNAND_GPMC_CONFIG6	0x1F0F0A80
349 #define SMNAND_GPMC_CONFIG7	0x00000C44
350 
351 #define M_NAND_GPMC_CONFIG1	0x00001800
352 #define M_NAND_GPMC_CONFIG2	0x00141400
353 #define M_NAND_GPMC_CONFIG3	0x00141400
354 #define M_NAND_GPMC_CONFIG4	0x0F010F01
355 #define M_NAND_GPMC_CONFIG5	0x010C1414
356 #define M_NAND_GPMC_CONFIG6	0x1f0f0A80
357 #define M_NAND_GPMC_CONFIG7	0x00000C44
358 
359 #define STNOR_GPMC_CONFIG1	0x3
360 #define STNOR_GPMC_CONFIG2	0x00151501
361 #define STNOR_GPMC_CONFIG3	0x00060602
362 #define STNOR_GPMC_CONFIG4	0x11091109
363 #define STNOR_GPMC_CONFIG5	0x01141F1F
364 #define STNOR_GPMC_CONFIG6	0x000004c4
365 
366 #define SIBNOR_GPMC_CONFIG1	0x1200
367 #define SIBNOR_GPMC_CONFIG2	0x001f1f00
368 #define SIBNOR_GPMC_CONFIG3	0x00080802
369 #define SIBNOR_GPMC_CONFIG4	0x1C091C09
370 #define SIBNOR_GPMC_CONFIG5	0x01131F1F
371 #define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
372 
373 #define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
374 #define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
375 #define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
376 #define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
377 #define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
378 #define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
379 
380 #define MPDB_GPMC_CONFIG1	0x00011000
381 #define MPDB_GPMC_CONFIG2	0x001f1f01
382 #define MPDB_GPMC_CONFIG3	0x00080803
383 #define MPDB_GPMC_CONFIG4	0x1c0b1c0a
384 #define MPDB_GPMC_CONFIG5	0x041f1F1F
385 #define MPDB_GPMC_CONFIG6	0x1F0F04C4
386 
387 #define P2_GPMC_CONFIG1	0x0
388 #define P2_GPMC_CONFIG2	0x0
389 #define P2_GPMC_CONFIG3	0x0
390 #define P2_GPMC_CONFIG4	0x0
391 #define P2_GPMC_CONFIG5	0x0
392 #define P2_GPMC_CONFIG6	0x0
393 
394 #define ONENAND_GPMC_CONFIG1	0x00001200
395 #define ONENAND_GPMC_CONFIG2	0x000F0F01
396 #define ONENAND_GPMC_CONFIG3	0x00030301
397 #define ONENAND_GPMC_CONFIG4	0x0F040F04
398 #define ONENAND_GPMC_CONFIG5	0x010F1010
399 #define ONENAND_GPMC_CONFIG6	0x1F060000
400 
401 #define NET_GPMC_CONFIG1	0x00001000
402 #define NET_GPMC_CONFIG2	0x001e1e01
403 #define NET_GPMC_CONFIG3	0x00080300
404 #define NET_GPMC_CONFIG4	0x1c091c09
405 #define NET_GPMC_CONFIG5	0x04181f1f
406 #define NET_GPMC_CONFIG6	0x00000FCF
407 #define NET_GPMC_CONFIG7	0x00000f6c
408 
409 /* max number of GPMC Chip Selects */
410 #define GPMC_MAX_CS	8
411 /* max number of GPMC regs */
412 #define GPMC_MAX_REG	7
413 
414 #define PISMO1_NOR	1
415 #define PISMO1_NAND	2
416 #define PISMO2_CS0	3
417 #define PISMO2_CS1	4
418 #define PISMO1_ONENAND	5
419 #define DBG_MPDB	6
420 #define PISMO2_NAND_CS0 7
421 #define PISMO2_NAND_CS1 8
422 
423 /* make it readable for the gpmc_init */
424 #define PISMO1_NOR_BASE		FLASH_BASE
425 #define PISMO1_NAND_BASE	NAND_BASE
426 #define PISMO2_CS0_BASE		PISMO2_MAP1
427 #define PISMO1_ONEN_BASE	ONENAND_MAP
428 #define DBG_MPDB_BASE		DEBUG_BASE
429 
430 #ifndef __ASSEMBLY__
431 
432 /* Function prototypes */
433 void mem_init(void);
434 
435 u32 is_mem_sdr(void);
436 u32 mem_ok(u32 cs);
437 
438 u32 get_sdr_cs_size(u32);
439 u32 get_sdr_cs_offset(u32);
440 
441 #endif	/* __ASSEMBLY__ */
442 
443 #endif /* endif _MEM_H_ */
444