1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* Slower full frequency range default timings for x32 operation*/ 43 #define SDRC_SHARING 0x00000100 44 #define SDRC_MR_0_SDR 0x00000031 45 46 #define DLL_OFFSET 0 47 #define DLL_WRITEDDRCLKX2DIS 1 48 #define DLL_ENADLL 1 49 #define DLL_LOCKDLL 0 50 #define DLL_DLLPHASE_72 0 51 #define DLL_DLLPHASE_90 1 52 53 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56 57 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns 58 * ACTIMA 59 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 60 * TDPL (Twr) = 15/6 = 2.5 -> 3 61 * TRRD = 12/6 = 2 62 * TRCD = 18/6 = 3 63 * TRP = 18/6 = 3 64 * TRAS = 42/6 = 7 65 * TRC = 60/6 = 10 66 * TRFC = 72/6 = 12 67 * ACTIMB 68 * TCKE = 2 69 * XSR = 120/6 = 20 70 */ 71 #define INFINEON_TDAL_165 6 72 #define INFINEON_TDPL_165 3 73 #define INFINEON_TRRD_165 2 74 #define INFINEON_TRCD_165 3 75 #define INFINEON_TRP_165 3 76 #define INFINEON_TRAS_165 7 77 #define INFINEON_TRC_165 10 78 #define INFINEON_TRFC_165 12 79 #define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ 80 (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ 81 (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ 82 (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ 83 (INFINEON_TDAL_165)) 84 85 #define INFINEON_TWTR_165 1 86 #define INFINEON_TCKE_165 2 87 #define INFINEON_TXP_165 2 88 #define INFINEON_XSR_165 20 89 #define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ 90 (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ 91 (INFINEON_TWTR_165 << 16)) 92 93 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns 94 * ACTIMA 95 * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 96 * TDPL (Twr) = 15/6 = 2.5 -> 3 97 * TRRD = 12/6 = 2 98 * TRCD = 18/6 = 3 99 * TRP = 18/6 = 3 100 * TRAS = 42/6 = 7 101 * TRC = 60/6 = 10 102 * TRFC = 125/6 = 21 103 * ACTIMB 104 * TWTR = 1 105 * TCKE = 1 106 * TXSR = 138/6 = 23 107 * TXP = 25/6 = 4.1 ~5 108 */ 109 #define MICRON_TDAL_165 6 110 #define MICRON_TDPL_165 3 111 #define MICRON_TRRD_165 2 112 #define MICRON_TRCD_165 3 113 #define MICRON_TRP_165 3 114 #define MICRON_TRAS_165 7 115 #define MICRON_TRC_165 10 116 #define MICRON_TRFC_165 21 117 #define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ 118 (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ 119 (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ 120 (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ 121 (MICRON_TDAL_165)) 122 123 #define MICRON_TWTR_165 1 124 #define MICRON_TCKE_165 1 125 #define MICRON_XSR_165 23 126 #define MICRON_TXP_165 5 127 #define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ 128 (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ 129 (MICRON_TWTR_165 << 16)) 130 131 #define MICRON_RAMTYPE 0x1 132 #define MICRON_DDRTYPE 0x0 133 #define MICRON_DEEPPD 0x1 134 #define MICRON_B32NOT16 0x1 135 #define MICRON_BANKALLOCATION 0x2 136 #define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) 137 #define MICRON_ADDRMUXLEGACY 0x1 138 #define MICRON_CASWIDTH 0x5 139 #define MICRON_RASWIDTH 0x2 140 #define MICRON_LOCKSTATUS 0x0 141 #define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ 142 (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ 143 (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ 144 (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ 145 (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) 146 147 #define MICRON_ARCV 2030 148 #define MICRON_ARE 0x1 149 #define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) 150 151 #define MICRON_BL 0x2 152 #define MICRON_SIL 0x0 153 #define MICRON_CASL 0x3 154 #define MICRON_WBST 0x0 155 #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ 156 (MICRON_SIL << 3) | (MICRON_BL)) 157 158 /* 159 * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns 160 * ACTIMA 161 * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 162 * TDPL (Twr) = 15/6 = 2.5 -> 3 163 * TRRD = 12/6 = 2 164 * TRCD = 22.5/6 = 3.75 -> 4 165 * TRP = 18/6 = 3 166 * TRAS = 42/6 = 7 167 * TRC = 60/6 = 10 168 * TRFC = 140/6 = 23.3 -> 24 169 * ACTIMB 170 * TWTR = 2 171 * TCKE = 2 172 * TXSR = 200/6 = 33.3 -> 34 173 * TXP = 1.0 + 1.1 = 2.1 -> 3 174 */ 175 #define NUMONYX_TDAL_165 6 176 #define NUMONYX_TDPL_165 3 177 #define NUMONYX_TRRD_165 2 178 #define NUMONYX_TRCD_165 4 179 #define NUMONYX_TRP_165 3 180 #define NUMONYX_TRAS_165 7 181 #define NUMONYX_TRC_165 10 182 #define NUMONYX_TRFC_165 24 183 #define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \ 184 (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \ 185 (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \ 186 (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \ 187 (NUMONYX_TDAL_165)) 188 189 #define NUMONYX_TWTR_165 2 190 #define NUMONYX_TCKE_165 2 191 #define NUMONYX_TXP_165 3 192 #define NUMONYX_XSR_165 34 193 #define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \ 194 (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ 195 (NUMONYX_TWTR_165 << 16)) 196 197 #ifdef CONFIG_OMAP3_INFINEON_DDR 198 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 199 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 200 #endif 201 202 #ifdef CONFIG_OMAP3_MICRON_DDR 203 #define V_ACTIMA_165 MICRON_V_ACTIMA_165 204 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 205 #define V_MCFG MICRON_V_MCFG 206 #define V_RFR_CTRL MICRON_V_RFR_CTRL 207 #define V_MR MICRON_V_MR 208 #endif 209 210 #ifdef CONFIG_OMAP3_NUMONYX_DDR 211 #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 212 #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 213 #endif 214 215 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 216 #error "Please choose the right DDR type in config header" 217 #endif 218 219 #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) 220 #error "Please choose the right DDR type in config header" 221 #endif 222 223 /* 224 * GPMC settings - 225 * Definitions is as per the following format 226 * #define <PART>_GPMC_CONFIG<x> <value> 227 * Where: 228 * PART is the part name e.g. STNOR - Intel Strata Flash 229 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 230 * Value is corresponding value 231 * 232 * For every valid PRCM configuration there should be only one definition of 233 * the same. if values are independent of the board, this definition will be 234 * present in this file if values are dependent on the board, then this should 235 * go into corresponding mem-boardName.h file 236 * 237 * Currently valid part Names are (PART): 238 * STNOR - Intel Strata Flash 239 * SMNAND - Samsung NAND 240 * MPDB - H4 MPDB board 241 * SBNOR - Sibley NOR 242 * MNAND - Micron Large page x16 NAND 243 * ONNAND - Samsung One NAND 244 * 245 * include/configs/file.h contains the defn - for all CS we are interested 246 * #define OMAP34XX_GPMC_CSx PART 247 * #define OMAP34XX_GPMC_CSx_SIZE Size 248 * #define OMAP34XX_GPMC_CSx_MAP Map 249 * Where: 250 * x - CS number 251 * PART - Part Name as defined above 252 * SIZE - how big is the mapping to be 253 * GPMC_SIZE_128M - 0x8 254 * GPMC_SIZE_64M - 0xC 255 * GPMC_SIZE_32M - 0xE 256 * GPMC_SIZE_16M - 0xF 257 * MAP - Map this CS to which address(GPMC address space)- Absolute address 258 * >>24 before being used. 259 */ 260 #define GPMC_SIZE_128M 0x8 261 #define GPMC_SIZE_64M 0xC 262 #define GPMC_SIZE_32M 0xE 263 #define GPMC_SIZE_16M 0xF 264 265 #define SMNAND_GPMC_CONFIG1 0x00000800 266 #define SMNAND_GPMC_CONFIG2 0x00141400 267 #define SMNAND_GPMC_CONFIG3 0x00141400 268 #define SMNAND_GPMC_CONFIG4 0x0F010F01 269 #define SMNAND_GPMC_CONFIG5 0x010C1414 270 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 271 #define SMNAND_GPMC_CONFIG7 0x00000C44 272 273 #define M_NAND_GPMC_CONFIG1 0x00001800 274 #define M_NAND_GPMC_CONFIG2 0x00141400 275 #define M_NAND_GPMC_CONFIG3 0x00141400 276 #define M_NAND_GPMC_CONFIG4 0x0F010F01 277 #define M_NAND_GPMC_CONFIG5 0x010C1414 278 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 279 #define M_NAND_GPMC_CONFIG7 0x00000C44 280 281 #define STNOR_GPMC_CONFIG1 0x3 282 #define STNOR_GPMC_CONFIG2 0x00151501 283 #define STNOR_GPMC_CONFIG3 0x00060602 284 #define STNOR_GPMC_CONFIG4 0x11091109 285 #define STNOR_GPMC_CONFIG5 0x01141F1F 286 #define STNOR_GPMC_CONFIG6 0x000004c4 287 288 #define SIBNOR_GPMC_CONFIG1 0x1200 289 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 290 #define SIBNOR_GPMC_CONFIG3 0x00080802 291 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 292 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 293 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 294 295 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 296 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 297 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 298 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 299 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 300 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 301 302 #define MPDB_GPMC_CONFIG1 0x00011000 303 #define MPDB_GPMC_CONFIG2 0x001f1f01 304 #define MPDB_GPMC_CONFIG3 0x00080803 305 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 306 #define MPDB_GPMC_CONFIG5 0x041f1F1F 307 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 308 309 #define P2_GPMC_CONFIG1 0x0 310 #define P2_GPMC_CONFIG2 0x0 311 #define P2_GPMC_CONFIG3 0x0 312 #define P2_GPMC_CONFIG4 0x0 313 #define P2_GPMC_CONFIG5 0x0 314 #define P2_GPMC_CONFIG6 0x0 315 316 #define ONENAND_GPMC_CONFIG1 0x00001200 317 #define ONENAND_GPMC_CONFIG2 0x000F0F01 318 #define ONENAND_GPMC_CONFIG3 0x00030301 319 #define ONENAND_GPMC_CONFIG4 0x0F040F04 320 #define ONENAND_GPMC_CONFIG5 0x010F1010 321 #define ONENAND_GPMC_CONFIG6 0x1F060000 322 323 #define NET_GPMC_CONFIG1 0x00001000 324 #define NET_GPMC_CONFIG2 0x001e1e01 325 #define NET_GPMC_CONFIG3 0x00080300 326 #define NET_GPMC_CONFIG4 0x1c091c09 327 #define NET_GPMC_CONFIG5 0x04181f1f 328 #define NET_GPMC_CONFIG6 0x00000FCF 329 #define NET_GPMC_CONFIG7 0x00000f6c 330 331 /* max number of GPMC Chip Selects */ 332 #define GPMC_MAX_CS 8 333 /* max number of GPMC regs */ 334 #define GPMC_MAX_REG 7 335 336 #define PISMO1_NOR 1 337 #define PISMO1_NAND 2 338 #define PISMO2_CS0 3 339 #define PISMO2_CS1 4 340 #define PISMO1_ONENAND 5 341 #define DBG_MPDB 6 342 #define PISMO2_NAND_CS0 7 343 #define PISMO2_NAND_CS1 8 344 345 /* make it readable for the gpmc_init */ 346 #define PISMO1_NOR_BASE FLASH_BASE 347 #define PISMO1_NAND_BASE NAND_BASE 348 #define PISMO2_CS0_BASE PISMO2_MAP1 349 #define PISMO1_ONEN_BASE ONENAND_MAP 350 #define DBG_MPDB_BASE DEBUG_BASE 351 352 #ifndef __ASSEMBLY__ 353 354 /* Function prototypes */ 355 void mem_init(void); 356 357 u32 is_mem_sdr(void); 358 u32 mem_ok(u32 cs); 359 360 u32 get_sdr_cs_size(u32); 361 u32 get_sdr_cs_offset(u32); 362 363 #endif /* __ASSEMBLY__ */ 364 365 #endif /* endif _MEM_H_ */ 366