1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* 43 * For a full explanation of these registers and values please see 44 * the Technical Reference Manual (TRM) for any of the processors in 45 * this family. 46 */ 47 48 /* Slower full frequency range default timings for x32 operation*/ 49 #define SDRC_SHARING 0x00000100 50 #define SDRC_MR_0_SDR 0x00000031 51 52 /* 53 * SDRC autorefresh control values. This register consists of autorefresh 54 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The 55 * counter is a result of ( tREFI / tCK ) - 50. 56 */ 57 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 58 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ 59 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ 60 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ 61 62 #define DLL_OFFSET 0 63 #define DLL_WRITEDDRCLKX2DIS 1 64 #define DLL_ENADLL 1 65 #define DLL_LOCKDLL 0 66 #define DLL_DLLPHASE_72 0 67 #define DLL_DLLPHASE_90 1 68 69 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 70 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 71 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 72 73 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 74 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 75 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 76 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 77 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 78 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 79 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 80 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 81 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 82 83 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ 84 ACTIM_CTRLA_TRFC(a) | \ 85 ACTIM_CTRLA_TRC(b) | \ 86 ACTIM_CTRLA_TRAS(b) | \ 87 ACTIM_CTRLA_TRP(d) | \ 88 ACTIM_CTRLA_TRCD(e) | \ 89 ACTIM_CTRLA_TRRD(f) | \ 90 ACTIM_CTRLA_TDPL(g) | \ 91 ACTIM_CTRLA_TDAL(h) 92 93 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 94 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 95 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 96 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 97 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 98 99 #define ACTIM_CTRLB(a,b,c,d) \ 100 ACTIM_CTRLB_TWTR(a) | \ 101 ACTIM_CTRLB_TCKE(b) | \ 102 ACTIM_CTRLB_TXP(b) | \ 103 ACTIM_CTRLB_TXSR(d) 104 105 /* 106 * Values used in the MCFG register. Only values we use today 107 * are defined and the rest can be found in the TRM. Unless otherwise 108 * noted all fields are one bit. 109 */ 110 #define V_MCFG_RAMTYPE_DDR (0x1) 111 #define V_MCFG_DEEPPD_EN (0x1 << 3) 112 #define V_MCFG_B32NOT16_32 (0x1 << 4) 113 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ 114 #define V_MCFG_RAMSIZE(a) ((((a)/(1024*1024))/2) << 8) /* 8:17 */ 115 #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) 116 #define V_MCFG_CASWIDTH_10B (0x5 << 20) /* 20:22 */ 117 #define V_MCFG_RASWIDTH(a) ((a) << 24) /* 24:26 */ 118 119 /* Macro to construct MCFG */ 120 #define MCFG(a, b) \ 121 V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B | \ 122 V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \ 123 V_MCFG_BANKALLOCATION_RBC | \ 124 V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR 125 126 /* Hynix part of AM/DM37xEVM (200MHz optimized) */ 127 #define HYNIX_TDAL_200 6 128 #define HYNIX_TDPL_200 3 129 #define HYNIX_TRRD_200 2 130 #define HYNIX_TRCD_200 4 131 #define HYNIX_TRP_200 3 132 #define HYNIX_TRAS_200 8 133 #define HYNIX_TRC_200 11 134 #define HYNIX_TRFC_200 18 135 #define HYNIX_V_ACTIMA_200 \ 136 ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ 137 HYNIX_TRAS_200, HYNIX_TRP_200, \ 138 HYNIX_TRCD_200, HYNIX_TRRD_200, \ 139 HYNIX_TDPL_200, HYNIX_TDAL_200) 140 141 #define HYNIX_TWTR_200 2 142 #define HYNIX_TCKE_200 1 143 #define HYNIX_TXP_200 1 144 #define HYNIX_XSR_200 28 145 #define HYNIX_V_ACTIMB_200 \ 146 ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ 147 HYNIX_TXP_200, HYNIX_XSR_200) 148 149 #define HYNIX_RASWIDTH_200 0x3 150 #define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) 151 152 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 153 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 154 /* 15/6 + 18/6 = 5.5 -> 6 */ 155 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 156 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 157 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 158 #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 159 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 160 #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 161 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 162 163 #define INFINEON_V_ACTIMA_165 \ 164 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 165 INFINEON_TRAS_165, INFINEON_TRP_165, \ 166 INFINEON_TRCD_165, INFINEON_TRRD_165, \ 167 INFINEON_TDPL_165, INFINEON_TDAL_165) 168 169 #define INFINEON_TWTR_165 1 170 #define INFINEON_TCKE_165 2 171 #define INFINEON_TXP_165 2 172 #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 173 174 #define INFINEON_V_ACTIMB_165 \ 175 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 176 INFINEON_TXP_165, INFINEON_XSR_165) 177 178 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 179 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 180 /* 15/6 + 18/6 = 5.5 -> 6 */ 181 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 182 #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 183 #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 184 #define MICRON_TRP_165 3 /* 18/6 = 3 */ 185 #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 186 #define MICRON_TRC_165 10 /* 60/6 = 10 */ 187 #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 188 189 #define MICRON_V_ACTIMA_165 \ 190 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 191 MICRON_TRAS_165, MICRON_TRP_165, \ 192 MICRON_TRCD_165, MICRON_TRRD_165, \ 193 MICRON_TDPL_165, MICRON_TDAL_165) 194 195 #define MICRON_TWTR_165 1 196 #define MICRON_TCKE_165 1 197 #define MICRON_XSR_165 23 /* 138/6 = 23 */ 198 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 199 200 #define MICRON_V_ACTIMB_165 \ 201 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 202 MICRON_TXP_165, MICRON_XSR_165) 203 204 #define MICRON_RASWIDTH_165 0x2 205 #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) 206 207 #define MICRON_BL_165 0x2 208 #define MICRON_SIL_165 0x0 209 #define MICRON_CASL_165 0x3 210 #define MICRON_WBST_165 0x0 211 #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ 212 (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ 213 (MICRON_BL_165)) 214 215 /* Micron part (200MHz optimized) 5 ns */ 216 #define MICRON_TDAL_200 6 217 #define MICRON_TDPL_200 3 218 #define MICRON_TRRD_200 2 219 #define MICRON_TRCD_200 3 220 #define MICRON_TRP_200 3 221 #define MICRON_TRAS_200 8 222 #define MICRON_TRC_200 11 223 #define MICRON_TRFC_200 15 224 #define MICRON_V_ACTIMA_200 \ 225 ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ 226 MICRON_TRAS_200, MICRON_TRP_200, \ 227 MICRON_TRCD_200, MICRON_TRRD_200, \ 228 MICRON_TDPL_200, MICRON_TDAL_200) 229 230 #define MICRON_TWTR_200 2 231 #define MICRON_TCKE_200 4 232 #define MICRON_TXP_200 2 233 #define MICRON_XSR_200 23 234 #define MICRON_V_ACTIMB_200 \ 235 ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ 236 MICRON_TXP_200, MICRON_XSR_200) 237 238 #define MICRON_RASWIDTH_200 0x3 239 #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) 240 241 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 242 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 243 /* 15/6 + 18/6 = 5.5 -> 6 */ 244 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 245 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 246 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 247 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 248 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 249 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 250 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 251 252 #define NUMONYX_V_ACTIMA_165 \ 253 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 254 NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 255 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 256 NUMONYX_TDPL_165, NUMONYX_TDAL_165) 257 258 #define NUMONYX_TWTR_165 2 259 #define NUMONYX_TCKE_165 2 260 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 261 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 262 263 #define NUMONYX_V_ACTIMB_165 \ 264 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 265 NUMONYX_TXP_165, NUMONYX_XSR_165) 266 267 #define NUMONYX_RASWIDTH_165 0x4 268 #define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) 269 270 /* 271 * GPMC settings - 272 * Definitions is as per the following format 273 * #define <PART>_GPMC_CONFIG<x> <value> 274 * Where: 275 * PART is the part name e.g. STNOR - Intel Strata Flash 276 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 277 * Value is corresponding value 278 * 279 * For every valid PRCM configuration there should be only one definition of 280 * the same. if values are independent of the board, this definition will be 281 * present in this file if values are dependent on the board, then this should 282 * go into corresponding mem-boardName.h file 283 * 284 * Currently valid part Names are (PART): 285 * STNOR - Intel Strata Flash 286 * SMNAND - Samsung NAND 287 * MPDB - H4 MPDB board 288 * SBNOR - Sibley NOR 289 * MNAND - Micron Large page x16 NAND 290 * ONNAND - Samsung One NAND 291 * 292 * include/configs/file.h contains the defn - for all CS we are interested 293 * #define OMAP34XX_GPMC_CSx PART 294 * #define OMAP34XX_GPMC_CSx_SIZE Size 295 * #define OMAP34XX_GPMC_CSx_MAP Map 296 * Where: 297 * x - CS number 298 * PART - Part Name as defined above 299 * SIZE - how big is the mapping to be 300 * GPMC_SIZE_128M - 0x8 301 * GPMC_SIZE_64M - 0xC 302 * GPMC_SIZE_32M - 0xE 303 * GPMC_SIZE_16M - 0xF 304 * MAP - Map this CS to which address(GPMC address space)- Absolute address 305 * >>24 before being used. 306 */ 307 #define GPMC_SIZE_128M 0x8 308 #define GPMC_SIZE_64M 0xC 309 #define GPMC_SIZE_32M 0xE 310 #define GPMC_SIZE_16M 0xF 311 312 #define GPMC_BASEADDR_MASK 0x3F 313 314 #define GPMC_CS_ENABLE 0x1 315 316 #define SMNAND_GPMC_CONFIG1 0x00000800 317 #define SMNAND_GPMC_CONFIG2 0x00141400 318 #define SMNAND_GPMC_CONFIG3 0x00141400 319 #define SMNAND_GPMC_CONFIG4 0x0F010F01 320 #define SMNAND_GPMC_CONFIG5 0x010C1414 321 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 322 #define SMNAND_GPMC_CONFIG7 0x00000C44 323 324 #define M_NAND_GPMC_CONFIG1 0x00001800 325 #define M_NAND_GPMC_CONFIG2 0x00141400 326 #define M_NAND_GPMC_CONFIG3 0x00141400 327 #define M_NAND_GPMC_CONFIG4 0x0F010F01 328 #define M_NAND_GPMC_CONFIG5 0x010C1414 329 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 330 #define M_NAND_GPMC_CONFIG7 0x00000C44 331 332 #define STNOR_GPMC_CONFIG1 0x3 333 #define STNOR_GPMC_CONFIG2 0x00151501 334 #define STNOR_GPMC_CONFIG3 0x00060602 335 #define STNOR_GPMC_CONFIG4 0x11091109 336 #define STNOR_GPMC_CONFIG5 0x01141F1F 337 #define STNOR_GPMC_CONFIG6 0x000004c4 338 339 #define SIBNOR_GPMC_CONFIG1 0x1200 340 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 341 #define SIBNOR_GPMC_CONFIG3 0x00080802 342 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 343 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 344 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 345 346 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 347 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 348 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 349 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 350 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 351 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 352 353 #define MPDB_GPMC_CONFIG1 0x00011000 354 #define MPDB_GPMC_CONFIG2 0x001f1f01 355 #define MPDB_GPMC_CONFIG3 0x00080803 356 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 357 #define MPDB_GPMC_CONFIG5 0x041f1F1F 358 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 359 360 #define P2_GPMC_CONFIG1 0x0 361 #define P2_GPMC_CONFIG2 0x0 362 #define P2_GPMC_CONFIG3 0x0 363 #define P2_GPMC_CONFIG4 0x0 364 #define P2_GPMC_CONFIG5 0x0 365 #define P2_GPMC_CONFIG6 0x0 366 367 #define ONENAND_GPMC_CONFIG1 0x00001200 368 #define ONENAND_GPMC_CONFIG2 0x000F0F01 369 #define ONENAND_GPMC_CONFIG3 0x00030301 370 #define ONENAND_GPMC_CONFIG4 0x0F040F04 371 #define ONENAND_GPMC_CONFIG5 0x010F1010 372 #define ONENAND_GPMC_CONFIG6 0x1F060000 373 374 #define NET_GPMC_CONFIG1 0x00001000 375 #define NET_GPMC_CONFIG2 0x001e1e01 376 #define NET_GPMC_CONFIG3 0x00080300 377 #define NET_GPMC_CONFIG4 0x1c091c09 378 #define NET_GPMC_CONFIG5 0x04181f1f 379 #define NET_GPMC_CONFIG6 0x00000FCF 380 #define NET_GPMC_CONFIG7 0x00000f6c 381 382 /* max number of GPMC Chip Selects */ 383 #define GPMC_MAX_CS 8 384 /* max number of GPMC regs */ 385 #define GPMC_MAX_REG 7 386 387 #define PISMO1_NOR 1 388 #define PISMO1_NAND 2 389 #define PISMO2_CS0 3 390 #define PISMO2_CS1 4 391 #define PISMO1_ONENAND 5 392 #define DBG_MPDB 6 393 #define PISMO2_NAND_CS0 7 394 #define PISMO2_NAND_CS1 8 395 396 /* make it readable for the gpmc_init */ 397 #define PISMO1_NOR_BASE FLASH_BASE 398 #define PISMO1_NAND_BASE NAND_BASE 399 #define PISMO2_CS0_BASE PISMO2_MAP1 400 #define PISMO1_ONEN_BASE ONENAND_MAP 401 #define DBG_MPDB_BASE DEBUG_BASE 402 403 #ifndef __ASSEMBLY__ 404 405 /* Function prototypes */ 406 void mem_init(void); 407 408 u32 is_mem_sdr(void); 409 u32 mem_ok(u32 cs); 410 411 u32 get_sdr_cs_size(u32); 412 u32 get_sdr_cs_offset(u32); 413 414 #endif /* __ASSEMBLY__ */ 415 416 #endif /* endif _MEM_H_ */ 417