1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _MEM_H_ 26 #define _MEM_H_ 27 28 #define CS0 0x0 29 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30 31 #ifndef __ASSEMBLY__ 32 enum { 33 STACKED = 0, 34 IP_DDR = 1, 35 COMBO_DDR = 2, 36 IP_SDR = 3, 37 }; 38 #endif /* __ASSEMBLY__ */ 39 40 #define EARLY_INIT 1 41 42 /* Slower full frequency range default timings for x32 operation*/ 43 #define SDRC_SHARING 0x00000100 44 #define SDRC_MR_0_SDR 0x00000031 45 46 #define DLL_OFFSET 0 47 #define DLL_WRITEDDRCLKX2DIS 1 48 #define DLL_ENADLL 1 49 #define DLL_LOCKDLL 0 50 #define DLL_DLLPHASE_72 0 51 #define DLL_DLLPHASE_90 1 52 53 /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54 #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55 (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56 57 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 58 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 59 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 60 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 61 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 62 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 63 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 64 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 65 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 66 67 #define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \ 68 ACTIM_CTRLA_TRFC(a) | \ 69 ACTIM_CTRLA_TRC(b) | \ 70 ACTIM_CTRLA_TRAS(b) | \ 71 ACTIM_CTRLA_TRP(d) | \ 72 ACTIM_CTRLA_TRCD(e) | \ 73 ACTIM_CTRLA_TRRD(f) | \ 74 ACTIM_CTRLA_TDPL(g) | \ 75 ACTIM_CTRLA_TDAL(h) 76 77 /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 78 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 79 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 80 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 81 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 82 83 #define ACTIM_CTRLB(a,b,c,d) \ 84 ACTIM_CTRLB_TWTR(a) | \ 85 ACTIM_CTRLB_TCKE(b) | \ 86 ACTIM_CTRLB_TXP(b) | \ 87 ACTIM_CTRLB_TXSR(d) 88 89 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 90 #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 91 /* 15/6 + 18/6 = 5.5 -> 6 */ 92 #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 93 #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 94 #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 95 #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 96 #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 97 #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 98 #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 99 100 #define INFINEON_V_ACTIMA_165 \ 101 ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 102 INFINEON_TRAS_165, INFINEON_TRP_165, \ 103 INFINEON_TRCD_165, INFINEON_TRRD_165, \ 104 INFINEON_TDPL_165, INFINEON_TDAL_165) 105 106 #define INFINEON_TWTR_165 1 107 #define INFINEON_TCKE_165 2 108 #define INFINEON_TXP_165 2 109 #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 110 111 #define INFINEON_V_ACTIMB_165 \ 112 ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 113 INFINEON_TXP_165, INFINEON_XSR_165) 114 115 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 116 #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 117 /* 15/6 + 18/6 = 5.5 -> 6 */ 118 #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 119 #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 120 #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 121 #define MICRON_TRP_165 3 /* 18/6 = 3 */ 122 #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 123 #define MICRON_TRC_165 10 /* 60/6 = 10 */ 124 #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 125 126 #define MICRON_V_ACTIMA_165 \ 127 ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 128 MICRON_TRAS_165, MICRON_TRP_165, \ 129 MICRON_TRCD_165, MICRON_TRRD_165, \ 130 MICRON_TDPL_165, MICRON_TDAL_165) 131 132 #define MICRON_TWTR_165 1 133 #define MICRON_TCKE_165 1 134 #define MICRON_XSR_165 23 /* 138/6 = 23 */ 135 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 136 137 #define MICRON_V_ACTIMB_165 \ 138 ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 139 MICRON_TXP_165, MICRON_XSR_165) 140 141 #define MICRON_RAMTYPE 0x1 142 #define MICRON_DDRTYPE 0x0 143 #define MICRON_DEEPPD 0x1 144 #define MICRON_B32NOT16 0x1 145 #define MICRON_BANKALLOCATION 0x2 146 #define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) 147 #define MICRON_ADDRMUXLEGACY 0x1 148 #define MICRON_CASWIDTH 0x5 149 #define MICRON_RASWIDTH 0x2 150 #define MICRON_LOCKSTATUS 0x0 151 #define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ 152 (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ 153 (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ 154 (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ 155 (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) 156 157 #define MICRON_ARCV 2030 158 #define MICRON_ARE 0x1 159 #define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) 160 161 #define MICRON_BL 0x2 162 #define MICRON_SIL 0x0 163 #define MICRON_CASL 0x3 164 #define MICRON_WBST 0x0 165 #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ 166 (MICRON_SIL << 3) | (MICRON_BL)) 167 168 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 169 #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 170 /* 15/6 + 18/6 = 5.5 -> 6 */ 171 #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 172 #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 173 #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 174 #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 175 #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 176 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 177 #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 178 179 #define NUMONYX_V_ACTIMA_165 \ 180 ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 181 NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 182 NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 183 NUMONYX_TDPL_165, NUMONYX_TDAL_165) 184 185 #define NUMONYX_TWTR_165 2 186 #define NUMONYX_TCKE_165 2 187 #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 188 #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 189 190 #define NUMONYX_V_ACTIMB_165 \ 191 ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 192 NUMONYX_TXP_165, NUMONYX_XSR_165) 193 194 #ifdef CONFIG_OMAP3_INFINEON_DDR 195 #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 196 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 197 #endif 198 199 #ifdef CONFIG_OMAP3_MICRON_DDR 200 #define V_ACTIMA_165 MICRON_V_ACTIMA_165 201 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 202 #define V_MCFG MICRON_V_MCFG 203 #define V_RFR_CTRL MICRON_V_RFR_CTRL 204 #define V_MR MICRON_V_MR 205 #endif 206 207 #ifdef CONFIG_OMAP3_NUMONYX_DDR 208 #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 209 #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 210 #endif 211 212 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 213 #error "Please choose the right DDR type in config header" 214 #endif 215 216 #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) 217 #error "Please choose the right DDR type in config header" 218 #endif 219 220 /* 221 * GPMC settings - 222 * Definitions is as per the following format 223 * #define <PART>_GPMC_CONFIG<x> <value> 224 * Where: 225 * PART is the part name e.g. STNOR - Intel Strata Flash 226 * x is GPMC config registers from 1 to 6 (there will be 6 macros) 227 * Value is corresponding value 228 * 229 * For every valid PRCM configuration there should be only one definition of 230 * the same. if values are independent of the board, this definition will be 231 * present in this file if values are dependent on the board, then this should 232 * go into corresponding mem-boardName.h file 233 * 234 * Currently valid part Names are (PART): 235 * STNOR - Intel Strata Flash 236 * SMNAND - Samsung NAND 237 * MPDB - H4 MPDB board 238 * SBNOR - Sibley NOR 239 * MNAND - Micron Large page x16 NAND 240 * ONNAND - Samsung One NAND 241 * 242 * include/configs/file.h contains the defn - for all CS we are interested 243 * #define OMAP34XX_GPMC_CSx PART 244 * #define OMAP34XX_GPMC_CSx_SIZE Size 245 * #define OMAP34XX_GPMC_CSx_MAP Map 246 * Where: 247 * x - CS number 248 * PART - Part Name as defined above 249 * SIZE - how big is the mapping to be 250 * GPMC_SIZE_128M - 0x8 251 * GPMC_SIZE_64M - 0xC 252 * GPMC_SIZE_32M - 0xE 253 * GPMC_SIZE_16M - 0xF 254 * MAP - Map this CS to which address(GPMC address space)- Absolute address 255 * >>24 before being used. 256 */ 257 #define GPMC_SIZE_128M 0x8 258 #define GPMC_SIZE_64M 0xC 259 #define GPMC_SIZE_32M 0xE 260 #define GPMC_SIZE_16M 0xF 261 262 #define SMNAND_GPMC_CONFIG1 0x00000800 263 #define SMNAND_GPMC_CONFIG2 0x00141400 264 #define SMNAND_GPMC_CONFIG3 0x00141400 265 #define SMNAND_GPMC_CONFIG4 0x0F010F01 266 #define SMNAND_GPMC_CONFIG5 0x010C1414 267 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 268 #define SMNAND_GPMC_CONFIG7 0x00000C44 269 270 #define M_NAND_GPMC_CONFIG1 0x00001800 271 #define M_NAND_GPMC_CONFIG2 0x00141400 272 #define M_NAND_GPMC_CONFIG3 0x00141400 273 #define M_NAND_GPMC_CONFIG4 0x0F010F01 274 #define M_NAND_GPMC_CONFIG5 0x010C1414 275 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 276 #define M_NAND_GPMC_CONFIG7 0x00000C44 277 278 #define STNOR_GPMC_CONFIG1 0x3 279 #define STNOR_GPMC_CONFIG2 0x00151501 280 #define STNOR_GPMC_CONFIG3 0x00060602 281 #define STNOR_GPMC_CONFIG4 0x11091109 282 #define STNOR_GPMC_CONFIG5 0x01141F1F 283 #define STNOR_GPMC_CONFIG6 0x000004c4 284 285 #define SIBNOR_GPMC_CONFIG1 0x1200 286 #define SIBNOR_GPMC_CONFIG2 0x001f1f00 287 #define SIBNOR_GPMC_CONFIG3 0x00080802 288 #define SIBNOR_GPMC_CONFIG4 0x1C091C09 289 #define SIBNOR_GPMC_CONFIG5 0x01131F1F 290 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 291 292 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 293 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 294 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 295 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 296 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 297 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 298 299 #define MPDB_GPMC_CONFIG1 0x00011000 300 #define MPDB_GPMC_CONFIG2 0x001f1f01 301 #define MPDB_GPMC_CONFIG3 0x00080803 302 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 303 #define MPDB_GPMC_CONFIG5 0x041f1F1F 304 #define MPDB_GPMC_CONFIG6 0x1F0F04C4 305 306 #define P2_GPMC_CONFIG1 0x0 307 #define P2_GPMC_CONFIG2 0x0 308 #define P2_GPMC_CONFIG3 0x0 309 #define P2_GPMC_CONFIG4 0x0 310 #define P2_GPMC_CONFIG5 0x0 311 #define P2_GPMC_CONFIG6 0x0 312 313 #define ONENAND_GPMC_CONFIG1 0x00001200 314 #define ONENAND_GPMC_CONFIG2 0x000F0F01 315 #define ONENAND_GPMC_CONFIG3 0x00030301 316 #define ONENAND_GPMC_CONFIG4 0x0F040F04 317 #define ONENAND_GPMC_CONFIG5 0x010F1010 318 #define ONENAND_GPMC_CONFIG6 0x1F060000 319 320 #define NET_GPMC_CONFIG1 0x00001000 321 #define NET_GPMC_CONFIG2 0x001e1e01 322 #define NET_GPMC_CONFIG3 0x00080300 323 #define NET_GPMC_CONFIG4 0x1c091c09 324 #define NET_GPMC_CONFIG5 0x04181f1f 325 #define NET_GPMC_CONFIG6 0x00000FCF 326 #define NET_GPMC_CONFIG7 0x00000f6c 327 328 /* max number of GPMC Chip Selects */ 329 #define GPMC_MAX_CS 8 330 /* max number of GPMC regs */ 331 #define GPMC_MAX_REG 7 332 333 #define PISMO1_NOR 1 334 #define PISMO1_NAND 2 335 #define PISMO2_CS0 3 336 #define PISMO2_CS1 4 337 #define PISMO1_ONENAND 5 338 #define DBG_MPDB 6 339 #define PISMO2_NAND_CS0 7 340 #define PISMO2_NAND_CS1 8 341 342 /* make it readable for the gpmc_init */ 343 #define PISMO1_NOR_BASE FLASH_BASE 344 #define PISMO1_NAND_BASE NAND_BASE 345 #define PISMO2_CS0_BASE PISMO2_MAP1 346 #define PISMO1_ONEN_BASE ONENAND_MAP 347 #define DBG_MPDB_BASE DEBUG_BASE 348 349 #ifndef __ASSEMBLY__ 350 351 /* Function prototypes */ 352 void mem_init(void); 353 354 u32 is_mem_sdr(void); 355 u32 mem_ok(u32 cs); 356 357 u32 get_sdr_cs_size(u32); 358 u32 get_sdr_cs_offset(u32); 359 360 #endif /* __ASSEMBLY__ */ 361 362 #endif /* endif _MEM_H_ */ 363