1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2006-2008 3819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 5819833afSPeter Tyser * 6819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 7819833afSPeter Tyser * project. 8819833afSPeter Tyser * 9819833afSPeter Tyser * This program is free software; you can redistribute it and/or 10819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 11819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 12819833afSPeter Tyser * the License, or (at your option) any later version. 13819833afSPeter Tyser * 14819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 15819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 16819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17819833afSPeter Tyser * GNU General Public License for more details. 18819833afSPeter Tyser * 19819833afSPeter Tyser * You should have received a copy of the GNU General Public License 20819833afSPeter Tyser * along with this program; if not, write to the Free Software 21819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22819833afSPeter Tyser * MA 02111-1307 USA 23819833afSPeter Tyser */ 24819833afSPeter Tyser 25819833afSPeter Tyser #ifndef _MEM_H_ 26819833afSPeter Tyser #define _MEM_H_ 27819833afSPeter Tyser 28819833afSPeter Tyser #define CS0 0x0 29819833afSPeter Tyser #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30819833afSPeter Tyser 31819833afSPeter Tyser #ifndef __ASSEMBLY__ 32819833afSPeter Tyser enum { 33819833afSPeter Tyser STACKED = 0, 34819833afSPeter Tyser IP_DDR = 1, 35819833afSPeter Tyser COMBO_DDR = 2, 36819833afSPeter Tyser IP_SDR = 3, 37819833afSPeter Tyser }; 38819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 39819833afSPeter Tyser 40819833afSPeter Tyser #define EARLY_INIT 1 41819833afSPeter Tyser 42819833afSPeter Tyser /* Slower full frequency range default timings for x32 operation*/ 43819833afSPeter Tyser #define SDRC_SHARING 0x00000100 44819833afSPeter Tyser #define SDRC_MR_0_SDR 0x00000031 45819833afSPeter Tyser 46819833afSPeter Tyser #define DLL_OFFSET 0 47819833afSPeter Tyser #define DLL_WRITEDDRCLKX2DIS 1 48819833afSPeter Tyser #define DLL_ENADLL 1 49819833afSPeter Tyser #define DLL_LOCKDLL 0 50819833afSPeter Tyser #define DLL_DLLPHASE_72 0 51819833afSPeter Tyser #define DLL_DLLPHASE_90 1 52819833afSPeter Tyser 53819833afSPeter Tyser /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54819833afSPeter Tyser #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55819833afSPeter Tyser (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56819833afSPeter Tyser 57819833afSPeter Tyser /* Infineon part of 3430SDP (165MHz optimized) 6.06ns 58819833afSPeter Tyser * ACTIMA 59819833afSPeter Tyser * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 60819833afSPeter Tyser * TDPL (Twr) = 15/6 = 2.5 -> 3 61819833afSPeter Tyser * TRRD = 12/6 = 2 62819833afSPeter Tyser * TRCD = 18/6 = 3 63819833afSPeter Tyser * TRP = 18/6 = 3 64819833afSPeter Tyser * TRAS = 42/6 = 7 65819833afSPeter Tyser * TRC = 60/6 = 10 66819833afSPeter Tyser * TRFC = 72/6 = 12 67819833afSPeter Tyser * ACTIMB 68819833afSPeter Tyser * TCKE = 2 69819833afSPeter Tyser * XSR = 120/6 = 20 70819833afSPeter Tyser */ 71819833afSPeter Tyser #define INFINEON_TDAL_165 6 72819833afSPeter Tyser #define INFINEON_TDPL_165 3 73819833afSPeter Tyser #define INFINEON_TRRD_165 2 74819833afSPeter Tyser #define INFINEON_TRCD_165 3 75819833afSPeter Tyser #define INFINEON_TRP_165 3 76819833afSPeter Tyser #define INFINEON_TRAS_165 7 77819833afSPeter Tyser #define INFINEON_TRC_165 10 78819833afSPeter Tyser #define INFINEON_TRFC_165 12 79819833afSPeter Tyser #define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ 80819833afSPeter Tyser (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ 81819833afSPeter Tyser (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ 82819833afSPeter Tyser (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ 83819833afSPeter Tyser (INFINEON_TDAL_165)) 84819833afSPeter Tyser 85819833afSPeter Tyser #define INFINEON_TWTR_165 1 86819833afSPeter Tyser #define INFINEON_TCKE_165 2 87819833afSPeter Tyser #define INFINEON_TXP_165 2 88819833afSPeter Tyser #define INFINEON_XSR_165 20 89819833afSPeter Tyser #define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ 90819833afSPeter Tyser (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ 91819833afSPeter Tyser (INFINEON_TWTR_165 << 16)) 92819833afSPeter Tyser 93819833afSPeter Tyser /* Micron part of 3430 EVM (165MHz optimized) 6.06ns 94819833afSPeter Tyser * ACTIMA 95819833afSPeter Tyser * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 96819833afSPeter Tyser * TDPL (Twr) = 15/6 = 2.5 -> 3 97819833afSPeter Tyser * TRRD = 12/6 = 2 98819833afSPeter Tyser * TRCD = 18/6 = 3 99819833afSPeter Tyser * TRP = 18/6 = 3 100819833afSPeter Tyser * TRAS = 42/6 = 7 101819833afSPeter Tyser * TRC = 60/6 = 10 102819833afSPeter Tyser * TRFC = 125/6 = 21 103819833afSPeter Tyser * ACTIMB 104819833afSPeter Tyser * TWTR = 1 105819833afSPeter Tyser * TCKE = 1 106819833afSPeter Tyser * TXSR = 138/6 = 23 107819833afSPeter Tyser * TXP = 25/6 = 4.1 ~5 108819833afSPeter Tyser */ 109819833afSPeter Tyser #define MICRON_TDAL_165 6 110819833afSPeter Tyser #define MICRON_TDPL_165 3 111819833afSPeter Tyser #define MICRON_TRRD_165 2 112819833afSPeter Tyser #define MICRON_TRCD_165 3 113819833afSPeter Tyser #define MICRON_TRP_165 3 114819833afSPeter Tyser #define MICRON_TRAS_165 7 115819833afSPeter Tyser #define MICRON_TRC_165 10 116819833afSPeter Tyser #define MICRON_TRFC_165 21 117819833afSPeter Tyser #define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ 118819833afSPeter Tyser (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ 119819833afSPeter Tyser (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ 120819833afSPeter Tyser (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ 121819833afSPeter Tyser (MICRON_TDAL_165)) 122819833afSPeter Tyser 123819833afSPeter Tyser #define MICRON_TWTR_165 1 124819833afSPeter Tyser #define MICRON_TCKE_165 1 125819833afSPeter Tyser #define MICRON_XSR_165 23 126819833afSPeter Tyser #define MICRON_TXP_165 5 127819833afSPeter Tyser #define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ 128819833afSPeter Tyser (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ 129819833afSPeter Tyser (MICRON_TWTR_165 << 16)) 130819833afSPeter Tyser 131*b88e4256SSimon Schwarz #define MICRON_RAMTYPE 0x1 132*b88e4256SSimon Schwarz #define MICRON_DDRTYPE 0x0 133*b88e4256SSimon Schwarz #define MICRON_DEEPPD 0x1 134*b88e4256SSimon Schwarz #define MICRON_B32NOT16 0x1 135*b88e4256SSimon Schwarz #define MICRON_BANKALLOCATION 0x2 136*b88e4256SSimon Schwarz #define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) 137*b88e4256SSimon Schwarz #define MICRON_ADDRMUXLEGACY 0x1 138*b88e4256SSimon Schwarz #define MICRON_CASWIDTH 0x5 139*b88e4256SSimon Schwarz #define MICRON_RASWIDTH 0x2 140*b88e4256SSimon Schwarz #define MICRON_LOCKSTATUS 0x0 141*b88e4256SSimon Schwarz #define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ 142*b88e4256SSimon Schwarz (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ 143*b88e4256SSimon Schwarz (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ 144*b88e4256SSimon Schwarz (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ 145*b88e4256SSimon Schwarz (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) 146*b88e4256SSimon Schwarz 147*b88e4256SSimon Schwarz #define MICRON_ARCV 2030 148*b88e4256SSimon Schwarz #define MICRON_ARE 0x1 149*b88e4256SSimon Schwarz #define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) 150*b88e4256SSimon Schwarz 151*b88e4256SSimon Schwarz #define MICRON_BL 0x2 152*b88e4256SSimon Schwarz #define MICRON_SIL 0x0 153*b88e4256SSimon Schwarz #define MICRON_CASL 0x3 154*b88e4256SSimon Schwarz #define MICRON_WBST 0x0 155*b88e4256SSimon Schwarz #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ 156*b88e4256SSimon Schwarz (MICRON_SIL << 3) | (MICRON_BL)) 157*b88e4256SSimon Schwarz 15884b66310SEnric Balletbo i Serra /* 15984b66310SEnric Balletbo i Serra * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns 16084b66310SEnric Balletbo i Serra * ACTIMA 16184b66310SEnric Balletbo i Serra * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 16284b66310SEnric Balletbo i Serra * TDPL (Twr) = 15/6 = 2.5 -> 3 16384b66310SEnric Balletbo i Serra * TRRD = 12/6 = 2 16484b66310SEnric Balletbo i Serra * TRCD = 22.5/6 = 3.75 -> 4 16584b66310SEnric Balletbo i Serra * TRP = 18/6 = 3 16684b66310SEnric Balletbo i Serra * TRAS = 42/6 = 7 16784b66310SEnric Balletbo i Serra * TRC = 60/6 = 10 16884b66310SEnric Balletbo i Serra * TRFC = 140/6 = 23.3 -> 24 16984b66310SEnric Balletbo i Serra * ACTIMB 17084b66310SEnric Balletbo i Serra * TWTR = 2 17184b66310SEnric Balletbo i Serra * TCKE = 2 17284b66310SEnric Balletbo i Serra * TXSR = 200/6 = 33.3 -> 34 17384b66310SEnric Balletbo i Serra * TXP = 1.0 + 1.1 = 2.1 -> 3 17484b66310SEnric Balletbo i Serra */ 17584b66310SEnric Balletbo i Serra #define NUMONYX_TDAL_165 6 17684b66310SEnric Balletbo i Serra #define NUMONYX_TDPL_165 3 17784b66310SEnric Balletbo i Serra #define NUMONYX_TRRD_165 2 17884b66310SEnric Balletbo i Serra #define NUMONYX_TRCD_165 4 17984b66310SEnric Balletbo i Serra #define NUMONYX_TRP_165 3 18084b66310SEnric Balletbo i Serra #define NUMONYX_TRAS_165 7 18184b66310SEnric Balletbo i Serra #define NUMONYX_TRC_165 10 18284b66310SEnric Balletbo i Serra #define NUMONYX_TRFC_165 24 18384b66310SEnric Balletbo i Serra #define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \ 18484b66310SEnric Balletbo i Serra (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \ 18584b66310SEnric Balletbo i Serra (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \ 18684b66310SEnric Balletbo i Serra (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \ 18784b66310SEnric Balletbo i Serra (NUMONYX_TDAL_165)) 18884b66310SEnric Balletbo i Serra 18984b66310SEnric Balletbo i Serra #define NUMONYX_TWTR_165 2 19084b66310SEnric Balletbo i Serra #define NUMONYX_TCKE_165 2 19184b66310SEnric Balletbo i Serra #define NUMONYX_TXP_165 3 19284b66310SEnric Balletbo i Serra #define NUMONYX_XSR_165 34 19384b66310SEnric Balletbo i Serra #define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \ 19484b66310SEnric Balletbo i Serra (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ 19584b66310SEnric Balletbo i Serra (NUMONYX_TWTR_165 << 16)) 19684b66310SEnric Balletbo i Serra 197819833afSPeter Tyser #ifdef CONFIG_OMAP3_INFINEON_DDR 198819833afSPeter Tyser #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 199819833afSPeter Tyser #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 200819833afSPeter Tyser #endif 201*b88e4256SSimon Schwarz 202819833afSPeter Tyser #ifdef CONFIG_OMAP3_MICRON_DDR 203819833afSPeter Tyser #define V_ACTIMA_165 MICRON_V_ACTIMA_165 204819833afSPeter Tyser #define V_ACTIMB_165 MICRON_V_ACTIMB_165 205*b88e4256SSimon Schwarz #define V_MCFG MICRON_V_MCFG 206*b88e4256SSimon Schwarz #define V_RFR_CTRL MICRON_V_RFR_CTRL 207*b88e4256SSimon Schwarz #define V_MR MICRON_V_MR 208819833afSPeter Tyser #endif 209*b88e4256SSimon Schwarz 21084b66310SEnric Balletbo i Serra #ifdef CONFIG_OMAP3_NUMONYX_DDR 21184b66310SEnric Balletbo i Serra #define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 21284b66310SEnric Balletbo i Serra #define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 21384b66310SEnric Balletbo i Serra #endif 214819833afSPeter Tyser 215819833afSPeter Tyser #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 216819833afSPeter Tyser #error "Please choose the right DDR type in config header" 217819833afSPeter Tyser #endif 218819833afSPeter Tyser 219*b88e4256SSimon Schwarz #if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) 220*b88e4256SSimon Schwarz #error "Please choose the right DDR type in config header" 221*b88e4256SSimon Schwarz #endif 222*b88e4256SSimon Schwarz 223819833afSPeter Tyser /* 224819833afSPeter Tyser * GPMC settings - 225819833afSPeter Tyser * Definitions is as per the following format 226819833afSPeter Tyser * #define <PART>_GPMC_CONFIG<x> <value> 227819833afSPeter Tyser * Where: 228819833afSPeter Tyser * PART is the part name e.g. STNOR - Intel Strata Flash 229819833afSPeter Tyser * x is GPMC config registers from 1 to 6 (there will be 6 macros) 230819833afSPeter Tyser * Value is corresponding value 231819833afSPeter Tyser * 232819833afSPeter Tyser * For every valid PRCM configuration there should be only one definition of 233819833afSPeter Tyser * the same. if values are independent of the board, this definition will be 234819833afSPeter Tyser * present in this file if values are dependent on the board, then this should 235819833afSPeter Tyser * go into corresponding mem-boardName.h file 236819833afSPeter Tyser * 237819833afSPeter Tyser * Currently valid part Names are (PART): 238819833afSPeter Tyser * STNOR - Intel Strata Flash 239819833afSPeter Tyser * SMNAND - Samsung NAND 240819833afSPeter Tyser * MPDB - H4 MPDB board 241819833afSPeter Tyser * SBNOR - Sibley NOR 242819833afSPeter Tyser * MNAND - Micron Large page x16 NAND 243819833afSPeter Tyser * ONNAND - Samsung One NAND 244819833afSPeter Tyser * 245819833afSPeter Tyser * include/configs/file.h contains the defn - for all CS we are interested 246819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx PART 247819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_SIZE Size 248819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_MAP Map 249819833afSPeter Tyser * Where: 250819833afSPeter Tyser * x - CS number 251819833afSPeter Tyser * PART - Part Name as defined above 252819833afSPeter Tyser * SIZE - how big is the mapping to be 253819833afSPeter Tyser * GPMC_SIZE_128M - 0x8 254819833afSPeter Tyser * GPMC_SIZE_64M - 0xC 255819833afSPeter Tyser * GPMC_SIZE_32M - 0xE 256819833afSPeter Tyser * GPMC_SIZE_16M - 0xF 257819833afSPeter Tyser * MAP - Map this CS to which address(GPMC address space)- Absolute address 258819833afSPeter Tyser * >>24 before being used. 259819833afSPeter Tyser */ 260819833afSPeter Tyser #define GPMC_SIZE_128M 0x8 261819833afSPeter Tyser #define GPMC_SIZE_64M 0xC 262819833afSPeter Tyser #define GPMC_SIZE_32M 0xE 263819833afSPeter Tyser #define GPMC_SIZE_16M 0xF 264819833afSPeter Tyser 265819833afSPeter Tyser #define SMNAND_GPMC_CONFIG1 0x00000800 266819833afSPeter Tyser #define SMNAND_GPMC_CONFIG2 0x00141400 267819833afSPeter Tyser #define SMNAND_GPMC_CONFIG3 0x00141400 268819833afSPeter Tyser #define SMNAND_GPMC_CONFIG4 0x0F010F01 269819833afSPeter Tyser #define SMNAND_GPMC_CONFIG5 0x010C1414 270819833afSPeter Tyser #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 271819833afSPeter Tyser #define SMNAND_GPMC_CONFIG7 0x00000C44 272819833afSPeter Tyser 273819833afSPeter Tyser #define M_NAND_GPMC_CONFIG1 0x00001800 274819833afSPeter Tyser #define M_NAND_GPMC_CONFIG2 0x00141400 275819833afSPeter Tyser #define M_NAND_GPMC_CONFIG3 0x00141400 276819833afSPeter Tyser #define M_NAND_GPMC_CONFIG4 0x0F010F01 277819833afSPeter Tyser #define M_NAND_GPMC_CONFIG5 0x010C1414 278819833afSPeter Tyser #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 279819833afSPeter Tyser #define M_NAND_GPMC_CONFIG7 0x00000C44 280819833afSPeter Tyser 281819833afSPeter Tyser #define STNOR_GPMC_CONFIG1 0x3 282819833afSPeter Tyser #define STNOR_GPMC_CONFIG2 0x00151501 283819833afSPeter Tyser #define STNOR_GPMC_CONFIG3 0x00060602 284819833afSPeter Tyser #define STNOR_GPMC_CONFIG4 0x11091109 285819833afSPeter Tyser #define STNOR_GPMC_CONFIG5 0x01141F1F 286819833afSPeter Tyser #define STNOR_GPMC_CONFIG6 0x000004c4 287819833afSPeter Tyser 288819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG1 0x1200 289819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG2 0x001f1f00 290819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG3 0x00080802 291819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG4 0x1C091C09 292819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG5 0x01131F1F 293819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 294819833afSPeter Tyser 295819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 296819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 297819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 298819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 299819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 300819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 301819833afSPeter Tyser 302819833afSPeter Tyser #define MPDB_GPMC_CONFIG1 0x00011000 303819833afSPeter Tyser #define MPDB_GPMC_CONFIG2 0x001f1f01 304819833afSPeter Tyser #define MPDB_GPMC_CONFIG3 0x00080803 305819833afSPeter Tyser #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 306819833afSPeter Tyser #define MPDB_GPMC_CONFIG5 0x041f1F1F 307819833afSPeter Tyser #define MPDB_GPMC_CONFIG6 0x1F0F04C4 308819833afSPeter Tyser 309819833afSPeter Tyser #define P2_GPMC_CONFIG1 0x0 310819833afSPeter Tyser #define P2_GPMC_CONFIG2 0x0 311819833afSPeter Tyser #define P2_GPMC_CONFIG3 0x0 312819833afSPeter Tyser #define P2_GPMC_CONFIG4 0x0 313819833afSPeter Tyser #define P2_GPMC_CONFIG5 0x0 314819833afSPeter Tyser #define P2_GPMC_CONFIG6 0x0 315819833afSPeter Tyser 316819833afSPeter Tyser #define ONENAND_GPMC_CONFIG1 0x00001200 317819833afSPeter Tyser #define ONENAND_GPMC_CONFIG2 0x000F0F01 318819833afSPeter Tyser #define ONENAND_GPMC_CONFIG3 0x00030301 319819833afSPeter Tyser #define ONENAND_GPMC_CONFIG4 0x0F040F04 320819833afSPeter Tyser #define ONENAND_GPMC_CONFIG5 0x010F1010 321819833afSPeter Tyser #define ONENAND_GPMC_CONFIG6 0x1F060000 322819833afSPeter Tyser 323819833afSPeter Tyser #define NET_GPMC_CONFIG1 0x00001000 324819833afSPeter Tyser #define NET_GPMC_CONFIG2 0x001e1e01 325819833afSPeter Tyser #define NET_GPMC_CONFIG3 0x00080300 326819833afSPeter Tyser #define NET_GPMC_CONFIG4 0x1c091c09 327819833afSPeter Tyser #define NET_GPMC_CONFIG5 0x04181f1f 328819833afSPeter Tyser #define NET_GPMC_CONFIG6 0x00000FCF 329819833afSPeter Tyser #define NET_GPMC_CONFIG7 0x00000f6c 330819833afSPeter Tyser 331819833afSPeter Tyser /* max number of GPMC Chip Selects */ 332819833afSPeter Tyser #define GPMC_MAX_CS 8 333819833afSPeter Tyser /* max number of GPMC regs */ 334819833afSPeter Tyser #define GPMC_MAX_REG 7 335819833afSPeter Tyser 336819833afSPeter Tyser #define PISMO1_NOR 1 337819833afSPeter Tyser #define PISMO1_NAND 2 338819833afSPeter Tyser #define PISMO2_CS0 3 339819833afSPeter Tyser #define PISMO2_CS1 4 340819833afSPeter Tyser #define PISMO1_ONENAND 5 341819833afSPeter Tyser #define DBG_MPDB 6 342819833afSPeter Tyser #define PISMO2_NAND_CS0 7 343819833afSPeter Tyser #define PISMO2_NAND_CS1 8 344819833afSPeter Tyser 345819833afSPeter Tyser /* make it readable for the gpmc_init */ 346819833afSPeter Tyser #define PISMO1_NOR_BASE FLASH_BASE 347819833afSPeter Tyser #define PISMO1_NAND_BASE NAND_BASE 348819833afSPeter Tyser #define PISMO2_CS0_BASE PISMO2_MAP1 349819833afSPeter Tyser #define PISMO1_ONEN_BASE ONENAND_MAP 350819833afSPeter Tyser #define DBG_MPDB_BASE DEBUG_BASE 351819833afSPeter Tyser 352cae377b5SVaibhav Hiremath #ifndef __ASSEMBLY__ 353cae377b5SVaibhav Hiremath 354cae377b5SVaibhav Hiremath /* Function prototypes */ 355cae377b5SVaibhav Hiremath void mem_init(void); 356cae377b5SVaibhav Hiremath 357cae377b5SVaibhav Hiremath u32 is_mem_sdr(void); 358cae377b5SVaibhav Hiremath u32 mem_ok(u32 cs); 359cae377b5SVaibhav Hiremath 360cae377b5SVaibhav Hiremath u32 get_sdr_cs_size(u32); 361cae377b5SVaibhav Hiremath u32 get_sdr_cs_offset(u32); 362cae377b5SVaibhav Hiremath 363cae377b5SVaibhav Hiremath #endif /* __ASSEMBLY__ */ 364cae377b5SVaibhav Hiremath 365819833afSPeter Tyser #endif /* endif _MEM_H_ */ 366