1*819833afSPeter Tyser /* 2*819833afSPeter Tyser * (C) Copyright 2006-2008 3*819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4*819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 5*819833afSPeter Tyser * 6*819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 7*819833afSPeter Tyser * project. 8*819833afSPeter Tyser * 9*819833afSPeter Tyser * This program is free software; you can redistribute it and/or 10*819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 11*819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 12*819833afSPeter Tyser * the License, or (at your option) any later version. 13*819833afSPeter Tyser * 14*819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 15*819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*819833afSPeter Tyser * GNU General Public License for more details. 18*819833afSPeter Tyser * 19*819833afSPeter Tyser * You should have received a copy of the GNU General Public License 20*819833afSPeter Tyser * along with this program; if not, write to the Free Software 21*819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*819833afSPeter Tyser * MA 02111-1307 USA 23*819833afSPeter Tyser */ 24*819833afSPeter Tyser 25*819833afSPeter Tyser #ifndef _MEM_H_ 26*819833afSPeter Tyser #define _MEM_H_ 27*819833afSPeter Tyser 28*819833afSPeter Tyser #define CS0 0x0 29*819833afSPeter Tyser #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 30*819833afSPeter Tyser 31*819833afSPeter Tyser #ifndef __ASSEMBLY__ 32*819833afSPeter Tyser enum { 33*819833afSPeter Tyser STACKED = 0, 34*819833afSPeter Tyser IP_DDR = 1, 35*819833afSPeter Tyser COMBO_DDR = 2, 36*819833afSPeter Tyser IP_SDR = 3, 37*819833afSPeter Tyser }; 38*819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 39*819833afSPeter Tyser 40*819833afSPeter Tyser #define EARLY_INIT 1 41*819833afSPeter Tyser 42*819833afSPeter Tyser /* Slower full frequency range default timings for x32 operation*/ 43*819833afSPeter Tyser #define SDRC_SHARING 0x00000100 44*819833afSPeter Tyser #define SDRC_MR_0_SDR 0x00000031 45*819833afSPeter Tyser 46*819833afSPeter Tyser #define DLL_OFFSET 0 47*819833afSPeter Tyser #define DLL_WRITEDDRCLKX2DIS 1 48*819833afSPeter Tyser #define DLL_ENADLL 1 49*819833afSPeter Tyser #define DLL_LOCKDLL 0 50*819833afSPeter Tyser #define DLL_DLLPHASE_72 0 51*819833afSPeter Tyser #define DLL_DLLPHASE_90 1 52*819833afSPeter Tyser 53*819833afSPeter Tyser /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54*819833afSPeter Tyser #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55*819833afSPeter Tyser (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56*819833afSPeter Tyser 57*819833afSPeter Tyser /* Infineon part of 3430SDP (165MHz optimized) 6.06ns 58*819833afSPeter Tyser * ACTIMA 59*819833afSPeter Tyser * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 60*819833afSPeter Tyser * TDPL (Twr) = 15/6 = 2.5 -> 3 61*819833afSPeter Tyser * TRRD = 12/6 = 2 62*819833afSPeter Tyser * TRCD = 18/6 = 3 63*819833afSPeter Tyser * TRP = 18/6 = 3 64*819833afSPeter Tyser * TRAS = 42/6 = 7 65*819833afSPeter Tyser * TRC = 60/6 = 10 66*819833afSPeter Tyser * TRFC = 72/6 = 12 67*819833afSPeter Tyser * ACTIMB 68*819833afSPeter Tyser * TCKE = 2 69*819833afSPeter Tyser * XSR = 120/6 = 20 70*819833afSPeter Tyser */ 71*819833afSPeter Tyser #define INFINEON_TDAL_165 6 72*819833afSPeter Tyser #define INFINEON_TDPL_165 3 73*819833afSPeter Tyser #define INFINEON_TRRD_165 2 74*819833afSPeter Tyser #define INFINEON_TRCD_165 3 75*819833afSPeter Tyser #define INFINEON_TRP_165 3 76*819833afSPeter Tyser #define INFINEON_TRAS_165 7 77*819833afSPeter Tyser #define INFINEON_TRC_165 10 78*819833afSPeter Tyser #define INFINEON_TRFC_165 12 79*819833afSPeter Tyser #define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ 80*819833afSPeter Tyser (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \ 81*819833afSPeter Tyser (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \ 82*819833afSPeter Tyser (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \ 83*819833afSPeter Tyser (INFINEON_TDAL_165)) 84*819833afSPeter Tyser 85*819833afSPeter Tyser #define INFINEON_TWTR_165 1 86*819833afSPeter Tyser #define INFINEON_TCKE_165 2 87*819833afSPeter Tyser #define INFINEON_TXP_165 2 88*819833afSPeter Tyser #define INFINEON_XSR_165 20 89*819833afSPeter Tyser #define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ 90*819833afSPeter Tyser (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \ 91*819833afSPeter Tyser (INFINEON_TWTR_165 << 16)) 92*819833afSPeter Tyser 93*819833afSPeter Tyser /* Micron part of 3430 EVM (165MHz optimized) 6.06ns 94*819833afSPeter Tyser * ACTIMA 95*819833afSPeter Tyser * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 96*819833afSPeter Tyser * TDPL (Twr) = 15/6 = 2.5 -> 3 97*819833afSPeter Tyser * TRRD = 12/6 = 2 98*819833afSPeter Tyser * TRCD = 18/6 = 3 99*819833afSPeter Tyser * TRP = 18/6 = 3 100*819833afSPeter Tyser * TRAS = 42/6 = 7 101*819833afSPeter Tyser * TRC = 60/6 = 10 102*819833afSPeter Tyser * TRFC = 125/6 = 21 103*819833afSPeter Tyser * ACTIMB 104*819833afSPeter Tyser * TWTR = 1 105*819833afSPeter Tyser * TCKE = 1 106*819833afSPeter Tyser * TXSR = 138/6 = 23 107*819833afSPeter Tyser * TXP = 25/6 = 4.1 ~5 108*819833afSPeter Tyser */ 109*819833afSPeter Tyser #define MICRON_TDAL_165 6 110*819833afSPeter Tyser #define MICRON_TDPL_165 3 111*819833afSPeter Tyser #define MICRON_TRRD_165 2 112*819833afSPeter Tyser #define MICRON_TRCD_165 3 113*819833afSPeter Tyser #define MICRON_TRP_165 3 114*819833afSPeter Tyser #define MICRON_TRAS_165 7 115*819833afSPeter Tyser #define MICRON_TRC_165 10 116*819833afSPeter Tyser #define MICRON_TRFC_165 21 117*819833afSPeter Tyser #define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ 118*819833afSPeter Tyser (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \ 119*819833afSPeter Tyser (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \ 120*819833afSPeter Tyser (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \ 121*819833afSPeter Tyser (MICRON_TDAL_165)) 122*819833afSPeter Tyser 123*819833afSPeter Tyser #define MICRON_TWTR_165 1 124*819833afSPeter Tyser #define MICRON_TCKE_165 1 125*819833afSPeter Tyser #define MICRON_XSR_165 23 126*819833afSPeter Tyser #define MICRON_TXP_165 5 127*819833afSPeter Tyser #define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ 128*819833afSPeter Tyser (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ 129*819833afSPeter Tyser (MICRON_TWTR_165 << 16)) 130*819833afSPeter Tyser 131*819833afSPeter Tyser #ifdef CONFIG_OMAP3_INFINEON_DDR 132*819833afSPeter Tyser #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 133*819833afSPeter Tyser #define V_ACTIMB_165 INFINEON_V_ACTIMB_165 134*819833afSPeter Tyser #endif 135*819833afSPeter Tyser #ifdef CONFIG_OMAP3_MICRON_DDR 136*819833afSPeter Tyser #define V_ACTIMA_165 MICRON_V_ACTIMA_165 137*819833afSPeter Tyser #define V_ACTIMB_165 MICRON_V_ACTIMB_165 138*819833afSPeter Tyser #endif 139*819833afSPeter Tyser 140*819833afSPeter Tyser #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) 141*819833afSPeter Tyser #error "Please choose the right DDR type in config header" 142*819833afSPeter Tyser #endif 143*819833afSPeter Tyser 144*819833afSPeter Tyser /* 145*819833afSPeter Tyser * GPMC settings - 146*819833afSPeter Tyser * Definitions is as per the following format 147*819833afSPeter Tyser * #define <PART>_GPMC_CONFIG<x> <value> 148*819833afSPeter Tyser * Where: 149*819833afSPeter Tyser * PART is the part name e.g. STNOR - Intel Strata Flash 150*819833afSPeter Tyser * x is GPMC config registers from 1 to 6 (there will be 6 macros) 151*819833afSPeter Tyser * Value is corresponding value 152*819833afSPeter Tyser * 153*819833afSPeter Tyser * For every valid PRCM configuration there should be only one definition of 154*819833afSPeter Tyser * the same. if values are independent of the board, this definition will be 155*819833afSPeter Tyser * present in this file if values are dependent on the board, then this should 156*819833afSPeter Tyser * go into corresponding mem-boardName.h file 157*819833afSPeter Tyser * 158*819833afSPeter Tyser * Currently valid part Names are (PART): 159*819833afSPeter Tyser * STNOR - Intel Strata Flash 160*819833afSPeter Tyser * SMNAND - Samsung NAND 161*819833afSPeter Tyser * MPDB - H4 MPDB board 162*819833afSPeter Tyser * SBNOR - Sibley NOR 163*819833afSPeter Tyser * MNAND - Micron Large page x16 NAND 164*819833afSPeter Tyser * ONNAND - Samsung One NAND 165*819833afSPeter Tyser * 166*819833afSPeter Tyser * include/configs/file.h contains the defn - for all CS we are interested 167*819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx PART 168*819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_SIZE Size 169*819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_MAP Map 170*819833afSPeter Tyser * Where: 171*819833afSPeter Tyser * x - CS number 172*819833afSPeter Tyser * PART - Part Name as defined above 173*819833afSPeter Tyser * SIZE - how big is the mapping to be 174*819833afSPeter Tyser * GPMC_SIZE_128M - 0x8 175*819833afSPeter Tyser * GPMC_SIZE_64M - 0xC 176*819833afSPeter Tyser * GPMC_SIZE_32M - 0xE 177*819833afSPeter Tyser * GPMC_SIZE_16M - 0xF 178*819833afSPeter Tyser * MAP - Map this CS to which address(GPMC address space)- Absolute address 179*819833afSPeter Tyser * >>24 before being used. 180*819833afSPeter Tyser */ 181*819833afSPeter Tyser #define GPMC_SIZE_128M 0x8 182*819833afSPeter Tyser #define GPMC_SIZE_64M 0xC 183*819833afSPeter Tyser #define GPMC_SIZE_32M 0xE 184*819833afSPeter Tyser #define GPMC_SIZE_16M 0xF 185*819833afSPeter Tyser 186*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG1 0x00000800 187*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG2 0x00141400 188*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG3 0x00141400 189*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG4 0x0F010F01 190*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG5 0x010C1414 191*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 192*819833afSPeter Tyser #define SMNAND_GPMC_CONFIG7 0x00000C44 193*819833afSPeter Tyser 194*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG1 0x00001800 195*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG2 0x00141400 196*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG3 0x00141400 197*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG4 0x0F010F01 198*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG5 0x010C1414 199*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 200*819833afSPeter Tyser #define M_NAND_GPMC_CONFIG7 0x00000C44 201*819833afSPeter Tyser 202*819833afSPeter Tyser #define STNOR_GPMC_CONFIG1 0x3 203*819833afSPeter Tyser #define STNOR_GPMC_CONFIG2 0x00151501 204*819833afSPeter Tyser #define STNOR_GPMC_CONFIG3 0x00060602 205*819833afSPeter Tyser #define STNOR_GPMC_CONFIG4 0x11091109 206*819833afSPeter Tyser #define STNOR_GPMC_CONFIG5 0x01141F1F 207*819833afSPeter Tyser #define STNOR_GPMC_CONFIG6 0x000004c4 208*819833afSPeter Tyser 209*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG1 0x1200 210*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG2 0x001f1f00 211*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG3 0x00080802 212*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG4 0x1C091C09 213*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG5 0x01131F1F 214*819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 215*819833afSPeter Tyser 216*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 217*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 218*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 219*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 220*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 221*819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 222*819833afSPeter Tyser 223*819833afSPeter Tyser #define MPDB_GPMC_CONFIG1 0x00011000 224*819833afSPeter Tyser #define MPDB_GPMC_CONFIG2 0x001f1f01 225*819833afSPeter Tyser #define MPDB_GPMC_CONFIG3 0x00080803 226*819833afSPeter Tyser #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 227*819833afSPeter Tyser #define MPDB_GPMC_CONFIG5 0x041f1F1F 228*819833afSPeter Tyser #define MPDB_GPMC_CONFIG6 0x1F0F04C4 229*819833afSPeter Tyser 230*819833afSPeter Tyser #define P2_GPMC_CONFIG1 0x0 231*819833afSPeter Tyser #define P2_GPMC_CONFIG2 0x0 232*819833afSPeter Tyser #define P2_GPMC_CONFIG3 0x0 233*819833afSPeter Tyser #define P2_GPMC_CONFIG4 0x0 234*819833afSPeter Tyser #define P2_GPMC_CONFIG5 0x0 235*819833afSPeter Tyser #define P2_GPMC_CONFIG6 0x0 236*819833afSPeter Tyser 237*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG1 0x00001200 238*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG2 0x000F0F01 239*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG3 0x00030301 240*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG4 0x0F040F04 241*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG5 0x010F1010 242*819833afSPeter Tyser #define ONENAND_GPMC_CONFIG6 0x1F060000 243*819833afSPeter Tyser 244*819833afSPeter Tyser #define NET_GPMC_CONFIG1 0x00001000 245*819833afSPeter Tyser #define NET_GPMC_CONFIG2 0x001e1e01 246*819833afSPeter Tyser #define NET_GPMC_CONFIG3 0x00080300 247*819833afSPeter Tyser #define NET_GPMC_CONFIG4 0x1c091c09 248*819833afSPeter Tyser #define NET_GPMC_CONFIG5 0x04181f1f 249*819833afSPeter Tyser #define NET_GPMC_CONFIG6 0x00000FCF 250*819833afSPeter Tyser #define NET_GPMC_CONFIG7 0x00000f6c 251*819833afSPeter Tyser 252*819833afSPeter Tyser /* max number of GPMC Chip Selects */ 253*819833afSPeter Tyser #define GPMC_MAX_CS 8 254*819833afSPeter Tyser /* max number of GPMC regs */ 255*819833afSPeter Tyser #define GPMC_MAX_REG 7 256*819833afSPeter Tyser 257*819833afSPeter Tyser #define PISMO1_NOR 1 258*819833afSPeter Tyser #define PISMO1_NAND 2 259*819833afSPeter Tyser #define PISMO2_CS0 3 260*819833afSPeter Tyser #define PISMO2_CS1 4 261*819833afSPeter Tyser #define PISMO1_ONENAND 5 262*819833afSPeter Tyser #define DBG_MPDB 6 263*819833afSPeter Tyser #define PISMO2_NAND_CS0 7 264*819833afSPeter Tyser #define PISMO2_NAND_CS1 8 265*819833afSPeter Tyser 266*819833afSPeter Tyser /* make it readable for the gpmc_init */ 267*819833afSPeter Tyser #define PISMO1_NOR_BASE FLASH_BASE 268*819833afSPeter Tyser #define PISMO1_NAND_BASE NAND_BASE 269*819833afSPeter Tyser #define PISMO2_CS0_BASE PISMO2_MAP1 270*819833afSPeter Tyser #define PISMO1_ONEN_BASE ONENAND_MAP 271*819833afSPeter Tyser #define DBG_MPDB_BASE DEBUG_BASE 272*819833afSPeter Tyser 273*819833afSPeter Tyser #endif /* endif _MEM_H_ */ 274