1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2006-2008 3819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4819833afSPeter Tyser * Richard Woodruff <r-woodruff2@ti.com> 5819833afSPeter Tyser * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7819833afSPeter Tyser */ 8819833afSPeter Tyser 9819833afSPeter Tyser #ifndef _MEM_H_ 10819833afSPeter Tyser #define _MEM_H_ 11819833afSPeter Tyser 12819833afSPeter Tyser #define CS0 0x0 13819833afSPeter Tyser #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ 14819833afSPeter Tyser 15819833afSPeter Tyser #ifndef __ASSEMBLY__ 16819833afSPeter Tyser enum { 17819833afSPeter Tyser STACKED = 0, 18819833afSPeter Tyser IP_DDR = 1, 19819833afSPeter Tyser COMBO_DDR = 2, 20819833afSPeter Tyser IP_SDR = 3, 21819833afSPeter Tyser }; 22819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 23819833afSPeter Tyser 24819833afSPeter Tyser #define EARLY_INIT 1 25819833afSPeter Tyser 2614ca3deeSTom Rini /* 2714ca3deeSTom Rini * For a full explanation of these registers and values please see 2814ca3deeSTom Rini * the Technical Reference Manual (TRM) for any of the processors in 2914ca3deeSTom Rini * this family. 3014ca3deeSTom Rini */ 3114ca3deeSTom Rini 32819833afSPeter Tyser /* Slower full frequency range default timings for x32 operation*/ 33819833afSPeter Tyser #define SDRC_SHARING 0x00000100 34819833afSPeter Tyser #define SDRC_MR_0_SDR 0x00000031 35819833afSPeter Tyser 361be1433bSTom Rini /* 371be1433bSTom Rini * SDRC autorefresh control values. This register consists of autorefresh 381be1433bSTom Rini * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The 391be1433bSTom Rini * counter is a result of ( tREFI / tCK ) - 50. 401be1433bSTom Rini */ 411be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 421be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ 431be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ 441be1433bSTom Rini #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ 451be1433bSTom Rini 46819833afSPeter Tyser #define DLL_OFFSET 0 47819833afSPeter Tyser #define DLL_WRITEDDRCLKX2DIS 1 48819833afSPeter Tyser #define DLL_ENADLL 1 49819833afSPeter Tyser #define DLL_LOCKDLL 0 50819833afSPeter Tyser #define DLL_DLLPHASE_72 0 51819833afSPeter Tyser #define DLL_DLLPHASE_90 1 52819833afSPeter Tyser 53819833afSPeter Tyser /* rkw - need to find of 90/72 degree recommendation for speed like before */ 54819833afSPeter Tyser #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ 55819833afSPeter Tyser (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) 56819833afSPeter Tyser 57e3596e35SSanjeev Premi /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */ 58e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */ 59e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */ 60e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */ 61e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */ 62e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */ 63e3596e35SSanjeev Premi #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */ 64e3596e35SSanjeev Premi #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */ 65e3596e35SSanjeev Premi #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */ 66e3596e35SSanjeev Premi 679540c7e9SPeter Barada #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ 689540c7e9SPeter Barada ACTIM_CTRLA_TRFC(trfc) | \ 699540c7e9SPeter Barada ACTIM_CTRLA_TRC(trc) | \ 709540c7e9SPeter Barada ACTIM_CTRLA_TRAS(tras) | \ 719540c7e9SPeter Barada ACTIM_CTRLA_TRP(trp) | \ 729540c7e9SPeter Barada ACTIM_CTRLA_TRCD(trcd) | \ 739540c7e9SPeter Barada ACTIM_CTRLA_TRRD(trrd) | \ 749540c7e9SPeter Barada ACTIM_CTRLA_TDPL(tdpl) | \ 759540c7e9SPeter Barada ACTIM_CTRLA_TDAL(tdal) 76e3596e35SSanjeev Premi 77e3596e35SSanjeev Premi /* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */ 78e3596e35SSanjeev Premi #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */ 79e3596e35SSanjeev Premi #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */ 80e3596e35SSanjeev Premi #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */ 81e3596e35SSanjeev Premi #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */ 82e3596e35SSanjeev Premi 839540c7e9SPeter Barada #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ 849540c7e9SPeter Barada ACTIM_CTRLB_TWTR(twtr) | \ 859540c7e9SPeter Barada ACTIM_CTRLB_TCKE(tcke) | \ 869540c7e9SPeter Barada ACTIM_CTRLB_TXP(txp) | \ 879540c7e9SPeter Barada ACTIM_CTRLB_TXSR(txsr) 88e3596e35SSanjeev Premi 8914ca3deeSTom Rini /* 9014ca3deeSTom Rini * Values used in the MCFG register. Only values we use today 9114ca3deeSTom Rini * are defined and the rest can be found in the TRM. Unless otherwise 9214ca3deeSTom Rini * noted all fields are one bit. 9314ca3deeSTom Rini */ 9414ca3deeSTom Rini #define V_MCFG_RAMTYPE_DDR (0x1) 9514ca3deeSTom Rini #define V_MCFG_DEEPPD_EN (0x1 << 3) 9614ca3deeSTom Rini #define V_MCFG_B32NOT16_32 (0x1 << 4) 9714ca3deeSTom Rini #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */ 989540c7e9SPeter Barada #define V_MCFG_RAMSIZE(ramsize) ((((ramsize) >> 20)/2) << 8) /* 8:17 */ 9914ca3deeSTom Rini #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19) 1009540c7e9SPeter Barada #define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */ 1019540c7e9SPeter Barada #define V_MCFG_CASWIDTH_10B V_MCFG_CASWIDTH(10) 1029540c7e9SPeter Barada #define V_MCFG_RASWIDTH(raswidth) (((raswidth)-11) << 24) /* 24:26 */ 10314ca3deeSTom Rini 10414ca3deeSTom Rini /* Macro to construct MCFG */ 1059540c7e9SPeter Barada #define MCFG(ramsize, raswidth) \ 1069540c7e9SPeter Barada V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B | \ 1079540c7e9SPeter Barada V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) | \ 1089540c7e9SPeter Barada V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 | \ 1099540c7e9SPeter Barada V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR 11014ca3deeSTom Rini 111137703b8SAndreas Müller /* Hynix part of Overo (165MHz optimized) 6.06ns */ 112137703b8SAndreas Müller #define HYNIX_TDAL_165 6 113137703b8SAndreas Müller #define HYNIX_TDPL_165 3 114137703b8SAndreas Müller #define HYNIX_TRRD_165 2 115137703b8SAndreas Müller #define HYNIX_TRCD_165 3 116137703b8SAndreas Müller #define HYNIX_TRP_165 3 117137703b8SAndreas Müller #define HYNIX_TRAS_165 7 118137703b8SAndreas Müller #define HYNIX_TRC_165 10 119137703b8SAndreas Müller #define HYNIX_TRFC_165 21 120137703b8SAndreas Müller #define HYNIX_V_ACTIMA_165 \ 121137703b8SAndreas Müller ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ 122137703b8SAndreas Müller HYNIX_TRAS_165, HYNIX_TRP_165, \ 123137703b8SAndreas Müller HYNIX_TRCD_165, HYNIX_TRRD_165, \ 124137703b8SAndreas Müller HYNIX_TDPL_165, HYNIX_TDAL_165) 125137703b8SAndreas Müller 126137703b8SAndreas Müller #define HYNIX_TWTR_165 1 127137703b8SAndreas Müller #define HYNIX_TCKE_165 1 128137703b8SAndreas Müller #define HYNIX_TXP_165 2 129137703b8SAndreas Müller #define HYNIX_XSR_165 24 130137703b8SAndreas Müller #define HYNIX_V_ACTIMB_165 \ 131137703b8SAndreas Müller ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ 132137703b8SAndreas Müller HYNIX_TXP_165, HYNIX_XSR_165) 133137703b8SAndreas Müller 1349540c7e9SPeter Barada #define HYNIX_RASWIDTH_165 13 135137703b8SAndreas Müller #define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) 136137703b8SAndreas Müller 137673283f3STom Rini /* Hynix part of AM/DM37xEVM (200MHz optimized) */ 138673283f3STom Rini #define HYNIX_TDAL_200 6 139673283f3STom Rini #define HYNIX_TDPL_200 3 140673283f3STom Rini #define HYNIX_TRRD_200 2 141673283f3STom Rini #define HYNIX_TRCD_200 4 142673283f3STom Rini #define HYNIX_TRP_200 3 143673283f3STom Rini #define HYNIX_TRAS_200 8 144673283f3STom Rini #define HYNIX_TRC_200 11 145673283f3STom Rini #define HYNIX_TRFC_200 18 146673283f3STom Rini #define HYNIX_V_ACTIMA_200 \ 147673283f3STom Rini ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ 148673283f3STom Rini HYNIX_TRAS_200, HYNIX_TRP_200, \ 149673283f3STom Rini HYNIX_TRCD_200, HYNIX_TRRD_200, \ 150673283f3STom Rini HYNIX_TDPL_200, HYNIX_TDAL_200) 151673283f3STom Rini 152673283f3STom Rini #define HYNIX_TWTR_200 2 153673283f3STom Rini #define HYNIX_TCKE_200 1 154673283f3STom Rini #define HYNIX_TXP_200 1 155673283f3STom Rini #define HYNIX_XSR_200 28 156673283f3STom Rini #define HYNIX_V_ACTIMB_200 \ 157673283f3STom Rini ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ 158673283f3STom Rini HYNIX_TXP_200, HYNIX_XSR_200) 159673283f3STom Rini 1609540c7e9SPeter Barada #define HYNIX_RASWIDTH_200 14 161673283f3STom Rini #define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200) 162673283f3STom Rini 1632c5b8756SSanjeev Premi /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ 1642c5b8756SSanjeev Premi #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 1652c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 1662c5b8756SSanjeev Premi #define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 1672c5b8756SSanjeev Premi #define INFINEON_TRRD_165 2 /* 12/6 = 2 */ 1682c5b8756SSanjeev Premi #define INFINEON_TRCD_165 3 /* 18/6 = 3 */ 1692c5b8756SSanjeev Premi #define INFINEON_TRP_165 3 /* 18/6 = 3 */ 1702c5b8756SSanjeev Premi #define INFINEON_TRAS_165 7 /* 42/6 = 7 */ 1712c5b8756SSanjeev Premi #define INFINEON_TRC_165 10 /* 60/6 = 10 */ 1722c5b8756SSanjeev Premi #define INFINEON_TRFC_165 12 /* 72/6 = 12 */ 173e3596e35SSanjeev Premi 174e3596e35SSanjeev Premi #define INFINEON_V_ACTIMA_165 \ 175e3596e35SSanjeev Premi ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \ 176e3596e35SSanjeev Premi INFINEON_TRAS_165, INFINEON_TRP_165, \ 177e3596e35SSanjeev Premi INFINEON_TRCD_165, INFINEON_TRRD_165, \ 178e3596e35SSanjeev Premi INFINEON_TDPL_165, INFINEON_TDAL_165) 179819833afSPeter Tyser 180819833afSPeter Tyser #define INFINEON_TWTR_165 1 181819833afSPeter Tyser #define INFINEON_TCKE_165 2 182819833afSPeter Tyser #define INFINEON_TXP_165 2 1832c5b8756SSanjeev Premi #define INFINEON_XSR_165 20 /* 120/6 = 20 */ 184e3596e35SSanjeev Premi 185e3596e35SSanjeev Premi #define INFINEON_V_ACTIMB_165 \ 186e3596e35SSanjeev Premi ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \ 187e3596e35SSanjeev Premi INFINEON_TXP_165, INFINEON_XSR_165) 188819833afSPeter Tyser 1892c5b8756SSanjeev Premi /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */ 1902c5b8756SSanjeev Premi #define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */ 1912c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 1922c5b8756SSanjeev Premi #define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 1932c5b8756SSanjeev Premi #define MICRON_TRRD_165 2 /* 12/6 = 2 */ 1942c5b8756SSanjeev Premi #define MICRON_TRCD_165 3 /* 18/6 = 3 */ 1952c5b8756SSanjeev Premi #define MICRON_TRP_165 3 /* 18/6 = 3 */ 1962c5b8756SSanjeev Premi #define MICRON_TRAS_165 7 /* 42/6 = 7 */ 1972c5b8756SSanjeev Premi #define MICRON_TRC_165 10 /* 60/6 = 10 */ 1982c5b8756SSanjeev Premi #define MICRON_TRFC_165 21 /* 125/6 = 21 */ 199e3596e35SSanjeev Premi 200e3596e35SSanjeev Premi #define MICRON_V_ACTIMA_165 \ 201e3596e35SSanjeev Premi ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \ 202e3596e35SSanjeev Premi MICRON_TRAS_165, MICRON_TRP_165, \ 203e3596e35SSanjeev Premi MICRON_TRCD_165, MICRON_TRRD_165, \ 204e3596e35SSanjeev Premi MICRON_TDPL_165, MICRON_TDAL_165) 205819833afSPeter Tyser 206819833afSPeter Tyser #define MICRON_TWTR_165 1 207819833afSPeter Tyser #define MICRON_TCKE_165 1 2082c5b8756SSanjeev Premi #define MICRON_XSR_165 23 /* 138/6 = 23 */ 2092c5b8756SSanjeev Premi #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */ 210e3596e35SSanjeev Premi 211e3596e35SSanjeev Premi #define MICRON_V_ACTIMB_165 \ 212e3596e35SSanjeev Premi ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \ 213e3596e35SSanjeev Premi MICRON_TXP_165, MICRON_XSR_165) 214819833afSPeter Tyser 2159540c7e9SPeter Barada #define MICRON_RASWIDTH_165 13 216fc41ba1eSTom Rini #define MICRON_V_MCFG_165(size) MCFG((size), MICRON_RASWIDTH_165) 217b88e4256SSimon Schwarz 218fc41ba1eSTom Rini #define MICRON_BL_165 0x2 219fc41ba1eSTom Rini #define MICRON_SIL_165 0x0 220fc41ba1eSTom Rini #define MICRON_CASL_165 0x3 221fc41ba1eSTom Rini #define MICRON_WBST_165 0x0 222fc41ba1eSTom Rini #define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ 223fc41ba1eSTom Rini (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ 224fc41ba1eSTom Rini (MICRON_BL_165)) 225b88e4256SSimon Schwarz 22675c57a35STom Rini /* Micron part (200MHz optimized) 5 ns */ 22775c57a35STom Rini #define MICRON_TDAL_200 6 22875c57a35STom Rini #define MICRON_TDPL_200 3 22975c57a35STom Rini #define MICRON_TRRD_200 2 23075c57a35STom Rini #define MICRON_TRCD_200 3 23175c57a35STom Rini #define MICRON_TRP_200 3 23275c57a35STom Rini #define MICRON_TRAS_200 8 23375c57a35STom Rini #define MICRON_TRC_200 11 23475c57a35STom Rini #define MICRON_TRFC_200 15 23575c57a35STom Rini #define MICRON_V_ACTIMA_200 \ 23675c57a35STom Rini ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \ 23775c57a35STom Rini MICRON_TRAS_200, MICRON_TRP_200, \ 23875c57a35STom Rini MICRON_TRCD_200, MICRON_TRRD_200, \ 23975c57a35STom Rini MICRON_TDPL_200, MICRON_TDAL_200) 24075c57a35STom Rini 24175c57a35STom Rini #define MICRON_TWTR_200 2 24275c57a35STom Rini #define MICRON_TCKE_200 4 24375c57a35STom Rini #define MICRON_TXP_200 2 24475c57a35STom Rini #define MICRON_XSR_200 23 24575c57a35STom Rini #define MICRON_V_ACTIMB_200 \ 24675c57a35STom Rini ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \ 24775c57a35STom Rini MICRON_TXP_200, MICRON_XSR_200) 24875c57a35STom Rini 2499540c7e9SPeter Barada #define MICRON_RASWIDTH_200 14 25075c57a35STom Rini #define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200) 25175c57a35STom Rini 2522c5b8756SSanjeev Premi /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */ 2532c5b8756SSanjeev Premi #define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */ 2542c5b8756SSanjeev Premi /* 15/6 + 18/6 = 5.5 -> 6 */ 2552c5b8756SSanjeev Premi #define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */ 2562c5b8756SSanjeev Premi #define NUMONYX_TRRD_165 2 /* 12/6 = 2 */ 2572c5b8756SSanjeev Premi #define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */ 2582c5b8756SSanjeev Premi #define NUMONYX_TRP_165 3 /* 18/6 = 3 */ 2592c5b8756SSanjeev Premi #define NUMONYX_TRAS_165 7 /* 42/6 = 7 */ 2602c5b8756SSanjeev Premi #define NUMONYX_TRC_165 10 /* 60/6 = 10 */ 2612c5b8756SSanjeev Premi #define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */ 262e3596e35SSanjeev Premi 263e3596e35SSanjeev Premi #define NUMONYX_V_ACTIMA_165 \ 264e3596e35SSanjeev Premi ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \ 265e3596e35SSanjeev Premi NUMONYX_TRAS_165, NUMONYX_TRP_165, \ 266e3596e35SSanjeev Premi NUMONYX_TRCD_165, NUMONYX_TRRD_165, \ 267e3596e35SSanjeev Premi NUMONYX_TDPL_165, NUMONYX_TDAL_165) 26884b66310SEnric Balletbo i Serra 26984b66310SEnric Balletbo i Serra #define NUMONYX_TWTR_165 2 27084b66310SEnric Balletbo i Serra #define NUMONYX_TCKE_165 2 2712c5b8756SSanjeev Premi #define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */ 2722c5b8756SSanjeev Premi #define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */ 273e3596e35SSanjeev Premi 274e3596e35SSanjeev Premi #define NUMONYX_V_ACTIMB_165 \ 275e3596e35SSanjeev Premi ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \ 276e3596e35SSanjeev Premi NUMONYX_TXP_165, NUMONYX_XSR_165) 27784b66310SEnric Balletbo i Serra 2789540c7e9SPeter Barada #define NUMONYX_RASWIDTH_165 15 27975c57a35STom Rini #define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165) 28075c57a35STom Rini 28141708a5dSJavier Martinez Canillas /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */ 28241708a5dSJavier Martinez Canillas #define NUMONYX_TDAL_200 6 /* Twr/Tck + Trp/tck */ 28341708a5dSJavier Martinez Canillas /* 15/5 + 15/5 = 3 + 3 -> 6 */ 28441708a5dSJavier Martinez Canillas #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */ 28541708a5dSJavier Martinez Canillas #define NUMONYX_TRRD_200 2 /* 10/5 = 2 */ 28641708a5dSJavier Martinez Canillas #define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */ 28741708a5dSJavier Martinez Canillas #define NUMONYX_TRP_200 3 /* 15/5 = 3 */ 28841708a5dSJavier Martinez Canillas #define NUMONYX_TRAS_200 8 /* 40/5 = 8 */ 28941708a5dSJavier Martinez Canillas #define NUMONYX_TRC_200 11 /* 55/5 = 11 */ 29041708a5dSJavier Martinez Canillas #define NUMONYX_TRFC_200 28 /* 140/5 = 28 */ 29141708a5dSJavier Martinez Canillas 29241708a5dSJavier Martinez Canillas #define NUMONYX_V_ACTIMA_200 \ 29341708a5dSJavier Martinez Canillas ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200, \ 29441708a5dSJavier Martinez Canillas NUMONYX_TRAS_200, NUMONYX_TRP_200, \ 29541708a5dSJavier Martinez Canillas NUMONYX_TRCD_200, NUMONYX_TRRD_200, \ 29641708a5dSJavier Martinez Canillas NUMONYX_TDPL_200, NUMONYX_TDAL_200) 29741708a5dSJavier Martinez Canillas 29841708a5dSJavier Martinez Canillas #define NUMONYX_TWTR_200 2 29941708a5dSJavier Martinez Canillas #define NUMONYX_TCKE_200 2 30041708a5dSJavier Martinez Canillas #define NUMONYX_TXP_200 3 30141708a5dSJavier Martinez Canillas #define NUMONYX_XSR_200 40 30241708a5dSJavier Martinez Canillas 30341708a5dSJavier Martinez Canillas #define NUMONYX_V_ACTIMB_200 \ 30441708a5dSJavier Martinez Canillas ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \ 30541708a5dSJavier Martinez Canillas NUMONYX_TXP_200, NUMONYX_XSR_200) 30641708a5dSJavier Martinez Canillas 30741708a5dSJavier Martinez Canillas #define NUMONYX_RASWIDTH_200 15 30841708a5dSJavier Martinez Canillas #define NUMONYX_V_MCFG_200(size) MCFG((size), NUMONYX_RASWIDTH_200) 30941708a5dSJavier Martinez Canillas 310819833afSPeter Tyser /* 311819833afSPeter Tyser * GPMC settings - 312819833afSPeter Tyser * Definitions is as per the following format 313819833afSPeter Tyser * #define <PART>_GPMC_CONFIG<x> <value> 314819833afSPeter Tyser * Where: 315819833afSPeter Tyser * PART is the part name e.g. STNOR - Intel Strata Flash 316819833afSPeter Tyser * x is GPMC config registers from 1 to 6 (there will be 6 macros) 317819833afSPeter Tyser * Value is corresponding value 318819833afSPeter Tyser * 319819833afSPeter Tyser * For every valid PRCM configuration there should be only one definition of 320819833afSPeter Tyser * the same. if values are independent of the board, this definition will be 321819833afSPeter Tyser * present in this file if values are dependent on the board, then this should 322819833afSPeter Tyser * go into corresponding mem-boardName.h file 323819833afSPeter Tyser * 324819833afSPeter Tyser * Currently valid part Names are (PART): 325819833afSPeter Tyser * STNOR - Intel Strata Flash 326819833afSPeter Tyser * SMNAND - Samsung NAND 327819833afSPeter Tyser * MPDB - H4 MPDB board 328819833afSPeter Tyser * SBNOR - Sibley NOR 329819833afSPeter Tyser * MNAND - Micron Large page x16 NAND 330819833afSPeter Tyser * ONNAND - Samsung One NAND 331819833afSPeter Tyser * 332819833afSPeter Tyser * include/configs/file.h contains the defn - for all CS we are interested 333819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx PART 334819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_SIZE Size 335819833afSPeter Tyser * #define OMAP34XX_GPMC_CSx_MAP Map 336819833afSPeter Tyser * Where: 337819833afSPeter Tyser * x - CS number 338819833afSPeter Tyser * PART - Part Name as defined above 339819833afSPeter Tyser * SIZE - how big is the mapping to be 340819833afSPeter Tyser * GPMC_SIZE_128M - 0x8 341819833afSPeter Tyser * GPMC_SIZE_64M - 0xC 342819833afSPeter Tyser * GPMC_SIZE_32M - 0xE 343819833afSPeter Tyser * GPMC_SIZE_16M - 0xF 344819833afSPeter Tyser * MAP - Map this CS to which address(GPMC address space)- Absolute address 345819833afSPeter Tyser * >>24 before being used. 346819833afSPeter Tyser */ 347819833afSPeter Tyser #define GPMC_SIZE_128M 0x8 348819833afSPeter Tyser #define GPMC_SIZE_64M 0xC 349819833afSPeter Tyser #define GPMC_SIZE_32M 0xE 350819833afSPeter Tyser #define GPMC_SIZE_16M 0xF 351819833afSPeter Tyser 352b7eb9e78STom Rini #define GPMC_BASEADDR_MASK 0x3F 353b7eb9e78STom Rini 354b7eb9e78STom Rini #define GPMC_CS_ENABLE 0x1 355b7eb9e78STom Rini 356819833afSPeter Tyser #define SMNAND_GPMC_CONFIG1 0x00000800 357819833afSPeter Tyser #define SMNAND_GPMC_CONFIG2 0x00141400 358819833afSPeter Tyser #define SMNAND_GPMC_CONFIG3 0x00141400 359819833afSPeter Tyser #define SMNAND_GPMC_CONFIG4 0x0F010F01 360819833afSPeter Tyser #define SMNAND_GPMC_CONFIG5 0x010C1414 361819833afSPeter Tyser #define SMNAND_GPMC_CONFIG6 0x1F0F0A80 362819833afSPeter Tyser #define SMNAND_GPMC_CONFIG7 0x00000C44 363819833afSPeter Tyser 364819833afSPeter Tyser #define M_NAND_GPMC_CONFIG1 0x00001800 365819833afSPeter Tyser #define M_NAND_GPMC_CONFIG2 0x00141400 366819833afSPeter Tyser #define M_NAND_GPMC_CONFIG3 0x00141400 367819833afSPeter Tyser #define M_NAND_GPMC_CONFIG4 0x0F010F01 368819833afSPeter Tyser #define M_NAND_GPMC_CONFIG5 0x010C1414 369819833afSPeter Tyser #define M_NAND_GPMC_CONFIG6 0x1f0f0A80 370819833afSPeter Tyser #define M_NAND_GPMC_CONFIG7 0x00000C44 371819833afSPeter Tyser 372819833afSPeter Tyser #define STNOR_GPMC_CONFIG1 0x3 373819833afSPeter Tyser #define STNOR_GPMC_CONFIG2 0x00151501 374819833afSPeter Tyser #define STNOR_GPMC_CONFIG3 0x00060602 375819833afSPeter Tyser #define STNOR_GPMC_CONFIG4 0x11091109 376819833afSPeter Tyser #define STNOR_GPMC_CONFIG5 0x01141F1F 377819833afSPeter Tyser #define STNOR_GPMC_CONFIG6 0x000004c4 378819833afSPeter Tyser 379819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG1 0x1200 380819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG2 0x001f1f00 381819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG3 0x00080802 382819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG4 0x1C091C09 383819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG5 0x01131F1F 384819833afSPeter Tyser #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 385819833afSPeter Tyser 386819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 387819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 388819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 389819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 390819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F 391819833afSPeter Tyser #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 392819833afSPeter Tyser 393819833afSPeter Tyser #define MPDB_GPMC_CONFIG1 0x00011000 394819833afSPeter Tyser #define MPDB_GPMC_CONFIG2 0x001f1f01 395819833afSPeter Tyser #define MPDB_GPMC_CONFIG3 0x00080803 396819833afSPeter Tyser #define MPDB_GPMC_CONFIG4 0x1c0b1c0a 397819833afSPeter Tyser #define MPDB_GPMC_CONFIG5 0x041f1F1F 398819833afSPeter Tyser #define MPDB_GPMC_CONFIG6 0x1F0F04C4 399819833afSPeter Tyser 400819833afSPeter Tyser #define P2_GPMC_CONFIG1 0x0 401819833afSPeter Tyser #define P2_GPMC_CONFIG2 0x0 402819833afSPeter Tyser #define P2_GPMC_CONFIG3 0x0 403819833afSPeter Tyser #define P2_GPMC_CONFIG4 0x0 404819833afSPeter Tyser #define P2_GPMC_CONFIG5 0x0 405819833afSPeter Tyser #define P2_GPMC_CONFIG6 0x0 406819833afSPeter Tyser 407819833afSPeter Tyser #define ONENAND_GPMC_CONFIG1 0x00001200 408819833afSPeter Tyser #define ONENAND_GPMC_CONFIG2 0x000F0F01 409819833afSPeter Tyser #define ONENAND_GPMC_CONFIG3 0x00030301 410819833afSPeter Tyser #define ONENAND_GPMC_CONFIG4 0x0F040F04 411819833afSPeter Tyser #define ONENAND_GPMC_CONFIG5 0x010F1010 412819833afSPeter Tyser #define ONENAND_GPMC_CONFIG6 0x1F060000 413819833afSPeter Tyser 414819833afSPeter Tyser #define NET_GPMC_CONFIG1 0x00001000 415819833afSPeter Tyser #define NET_GPMC_CONFIG2 0x001e1e01 416819833afSPeter Tyser #define NET_GPMC_CONFIG3 0x00080300 417819833afSPeter Tyser #define NET_GPMC_CONFIG4 0x1c091c09 418819833afSPeter Tyser #define NET_GPMC_CONFIG5 0x04181f1f 419819833afSPeter Tyser #define NET_GPMC_CONFIG6 0x00000FCF 420819833afSPeter Tyser #define NET_GPMC_CONFIG7 0x00000f6c 421819833afSPeter Tyser 422819833afSPeter Tyser /* max number of GPMC Chip Selects */ 423819833afSPeter Tyser #define GPMC_MAX_CS 8 424819833afSPeter Tyser /* max number of GPMC regs */ 425819833afSPeter Tyser #define GPMC_MAX_REG 7 426819833afSPeter Tyser 427819833afSPeter Tyser #define PISMO1_NOR 1 428819833afSPeter Tyser #define PISMO1_NAND 2 429819833afSPeter Tyser #define PISMO2_CS0 3 430819833afSPeter Tyser #define PISMO2_CS1 4 431819833afSPeter Tyser #define PISMO1_ONENAND 5 432819833afSPeter Tyser #define DBG_MPDB 6 433819833afSPeter Tyser #define PISMO2_NAND_CS0 7 434819833afSPeter Tyser #define PISMO2_NAND_CS1 8 435819833afSPeter Tyser 436819833afSPeter Tyser /* make it readable for the gpmc_init */ 437819833afSPeter Tyser #define PISMO1_NOR_BASE FLASH_BASE 438819833afSPeter Tyser #define PISMO1_NAND_BASE NAND_BASE 439819833afSPeter Tyser #define PISMO2_CS0_BASE PISMO2_MAP1 440819833afSPeter Tyser #define PISMO1_ONEN_BASE ONENAND_MAP 441819833afSPeter Tyser #define DBG_MPDB_BASE DEBUG_BASE 442819833afSPeter Tyser 443cae377b5SVaibhav Hiremath #ifndef __ASSEMBLY__ 444cae377b5SVaibhav Hiremath 445cae377b5SVaibhav Hiremath /* Function prototypes */ 446cae377b5SVaibhav Hiremath void mem_init(void); 447cae377b5SVaibhav Hiremath 448cae377b5SVaibhav Hiremath u32 is_mem_sdr(void); 449cae377b5SVaibhav Hiremath u32 mem_ok(u32 cs); 450cae377b5SVaibhav Hiremath 451cae377b5SVaibhav Hiremath u32 get_sdr_cs_size(u32); 452cae377b5SVaibhav Hiremath u32 get_sdr_cs_offset(u32); 453cae377b5SVaibhav Hiremath 454cae377b5SVaibhav Hiremath #endif /* __ASSEMBLY__ */ 455cae377b5SVaibhav Hiremath 456819833afSPeter Tyser #endif /* endif _MEM_H_ */ 457