1 /*
2  * (C) Copyright 2010
3  * Texas Instruments, <www.ti.com>
4  * Syed Mohammed Khasim <khasim@ti.com>
5  *
6  * Referred to Linux Kernel DSS driver files for OMAP3 by
7  * Tomi Valkeinen from drivers/video/omap2/dss/
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation's version 2 and any
15  * later version the License.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27 
28 #ifndef DSS_H
29 #define DSS_H
30 
31 /* DSS Base Registers */
32 #define OMAP3_DSS_BASE		0x48050000
33 #define OMAP3_DISPC_BASE	0x48050400
34 #define OMAP3_VENC_BASE		0x48050C00
35 
36 /* DSS Registers */
37 struct dss_regs {
38 	u32 revision;				/* 0x00 */
39 	u8 res1[12];				/* 0x04 */
40 	u32 sysconfig;				/* 0x10 */
41 	u32 sysstatus;				/* 0x14 */
42 	u32 irqstatus;				/* 0x18 */
43 	u8 res2[36];				/* 0x1C */
44 	u32 control;				/* 0x40 */
45 	u32 sdi_control;			/* 0x44 */
46 	u32 pll_control;			/* 0x48 */
47 };
48 
49 /* DISPC Registers */
50 struct dispc_regs {
51 	u32 revision;				/* 0x00 */
52 	u8 res1[12];				/* 0x04 */
53 	u32 sysconfig;				/* 0x10 */
54 	u32 sysstatus;				/* 0x14 */
55 	u32 irqstatus;				/* 0x18 */
56 	u32 irqenable;				/* 0x1C */
57 	u8 res2[32];				/* 0x20 */
58 	u32 control;				/* 0x40 */
59 	u32 config;				/* 0x44 */
60 	u32 reserve_2;				/* 0x48 */
61 	u32 default_color0;			/* 0x4C */
62 	u32 default_color1;			/* 0x50 */
63 	u32 trans_color0;			/* 0x54 */
64 	u32 trans_color1;			/* 0x58 */
65 	u32 line_status;			/* 0x5C */
66 	u32 line_number;			/* 0x60 */
67 	u32 timing_h;				/* 0x64 */
68 	u32 timing_v;				/* 0x68 */
69 	u32 pol_freq;				/* 0x6C */
70 	u32 divisor;				/* 0x70 */
71 	u32 global_alpha;			/* 0x74 */
72 	u32 size_dig;				/* 0x78 */
73 	u32 size_lcd;				/* 0x7C */
74 	u32 gfx_ba0;				/* 0x80 */
75 	u32 gfx_ba1;				/* 0x84 */
76 	u32 gfx_position;			/* 0x88 */
77 	u32 gfx_size;				/* 0x8C */
78 	u8 unused[16];				/* 0x90 */
79 	u32 gfx_attributes;			/* 0xA0 */
80 	u32 gfx_fifo_threshold;			/* 0xA4 */
81 	u32 gfx_fifo_size_status;		/* 0xA8 */
82 	u32 gfx_row_inc;			/* 0xAC */
83 	u32 gfx_pixel_inc;			/* 0xB0 */
84 	u32 gfx_window_skip;			/* 0xB4 */
85 	u32 gfx_table_ba;			/* 0xB8 */
86 };
87 
88 /* VENC Registers */
89 struct venc_regs {
90 	u32 rev_id;				/* 0x00 */
91 	u32 status;				/* 0x04 */
92 	u32 f_control;				/* 0x08 */
93 	u32 reserve_1;				/* 0x0C */
94 	u32 vidout_ctrl;			/* 0x10 */
95 	u32 sync_ctrl;				/* 0x14 */
96 	u32 reserve_2;				/* 0x18 */
97 	u32 llen;				/* 0x1C */
98 	u32 flens;				/* 0x20 */
99 	u32 hfltr_ctrl;				/* 0x24 */
100 	u32 cc_carr_wss_carr;			/* 0x28 */
101 	u32 c_phase;				/* 0x2C */
102 	u32 gain_u;				/* 0x30 */
103 	u32 gain_v;				/* 0x34 */
104 	u32 gain_y;				/* 0x38 */
105 	u32 black_level;			/* 0x3C */
106 	u32 blank_level;			/* 0x40 */
107 	u32 x_color;				/* 0x44 */
108 	u32 m_control;				/* 0x48 */
109 	u32 bstamp_wss_data;			/* 0x4C */
110 	u32 s_carr;				/* 0x50 */
111 	u32 line21;				/* 0x54 */
112 	u32 ln_sel;				/* 0x58 */
113 	u32 l21__wc_ctl;			/* 0x5C */
114 	u32 htrigger_vtrigger;			/* 0x60 */
115 	u32 savid__eavid;			/* 0x64 */
116 	u32 flen__fal;				/* 0x68 */
117 	u32 lal__phase_reset;			/* 0x6C */
118 	u32 hs_int_start_stop_x;		/* 0x70 */
119 	u32 hs_ext_start_stop_x;		/* 0x74 */
120 	u32 vs_int_start_x;			/* 0x78 */
121 	u32 vs_int_stop_x__vs_int_start_y;	/* 0x7C */
122 	u32 vs_int_stop_y__vs_ext_start_x;	/* 0x80 */
123 	u32 vs_ext_stop_x__vs_ext_start_y;	/* 0x84 */
124 	u32 vs_ext_stop_y;			/* 0x88 */
125 	u32 reserve_3;				/* 0x8C */
126 	u32 avid_start_stop_x;			/* 0x90 */
127 	u32 avid_start_stop_y;			/* 0x94 */
128 	u32 reserve_4;				/* 0x98 */
129 	u32 reserve_5;				/* 0x9C */
130 	u32 fid_int_start_x__fid_int_start_y;	/* 0xA0 */
131 	u32 fid_int_offset_y__fid_ext_start_x;	/* 0xA4 */
132 	u32 fid_ext_start_y__fid_ext_offset_y;	/* 0xA8 */
133 	u32 reserve_6;				/* 0xAC */
134 	u32 tvdetgp_int_start_stop_x;		/* 0xB0 */
135 	u32 tvdetgp_int_start_stop_y;		/* 0xB4 */
136 	u32 gen_ctrl;				/* 0xB8 */
137 	u32 reserve_7;				/* 0xBC */
138 	u32 reserve_8;				/* 0xC0 */
139 	u32 output_control;			/* 0xC4 */
140 	u32 dac_b__dac_c;			/* 0xC8 */
141 	u32 height_width;			/* 0xCC */
142 };
143 
144 /* Few Register Offsets */
145 #define FRAME_MODE_SHIFT			1
146 #define TFTSTN_SHIFT				3
147 #define DATALINES_SHIFT				8
148 
149 #define GFX_ENABLE				1
150 #define GFX_FORMAT_SHIFT			1
151 #define LOADMODE_SHIFT				1
152 
153 #define DSS_SOFTRESET				(1 << 1)
154 #define DSS_RESETDONE				1
155 
156 /* Enabling Display controller */
157 #define LCD_ENABLE				1
158 #define DIG_ENABLE				(1 << 1)
159 #define GO_LCD					(1 << 5)
160 #define GO_DIG					(1 << 6)
161 #define GP_OUT0					(1 << 15)
162 #define GP_OUT1					(1 << 16)
163 
164 /* Configure VENC DSS Params */
165 #define VENC_CLK_ENABLE				(1 << 3)
166 #define DAC_DEMEN				(1 << 4)
167 #define DAC_POWERDN				(1 << 5)
168 #define VENC_OUT_SEL				(1 << 6)
169 #define DIG_LPP_SHIFT				16
170 
171 /* Panel Configuration */
172 struct panel_config {
173 	u32 timing_h;
174 	u32 timing_v;
175 	u32 pol_freq;
176 	u32 divisor;
177 	u32 lcd_size;
178 	u32 panel_type;
179 	u32 data_lines;
180 	u32 load_mode;
181 	u32 panel_color;
182 	void *frame_buffer;
183 };
184 
185 /* Generic DSS Functions */
186 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
187 			u32 height, u32 width);
188 void omap3_dss_panel_config(const struct panel_config *panel_cfg);
189 void omap3_dss_enable(void);
190 
191 #endif /* DSS_H */
192