1 /* 2 * (C) Copyright 2010 3 * Texas Instruments, <www.ti.com> 4 * Syed Mohammed Khasim <khasim@ti.com> 5 * 6 * Referred to Linux Kernel DSS driver files for OMAP3 by 7 * Tomi Valkeinen from drivers/video/omap2/dss/ 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation's version 2 and any 15 * later version the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef DSS_H 29 #define DSS_H 30 31 /* 32 * DSS Base Registers 33 */ 34 #define OMAP3_DSS_BASE 0x48050040 35 #define OMAP3_DISPC_BASE 0x48050440 36 #define OMAP3_VENC_BASE 0x48050C00 37 38 /* DSS Registers */ 39 struct dss_regs { 40 u32 control; /* 0x40 */ 41 u32 sdi_control; /* 0x44 */ 42 u32 pll_control; /* 0x48 */ 43 }; 44 45 /* DISPC Registers */ 46 struct dispc_regs { 47 u32 control; /* 0x40 */ 48 u32 config; /* 0x44 */ 49 u32 reserve_2; /* 0x48 */ 50 u32 default_color0; /* 0x4C */ 51 u32 default_color1; /* 0x50 */ 52 u32 trans_color0; /* 0x54 */ 53 u32 trans_color1; /* 0x58 */ 54 u32 line_status; /* 0x5C */ 55 u32 line_number; /* 0x60 */ 56 u32 timing_h; /* 0x64 */ 57 u32 timing_v; /* 0x68 */ 58 u32 pol_freq; /* 0x6C */ 59 u32 divisor; /* 0x70 */ 60 u32 global_alpha; /* 0x74 */ 61 u32 size_dig; /* 0x78 */ 62 u32 size_lcd; /* 0x7C */ 63 }; 64 65 /* VENC Registers */ 66 struct venc_regs { 67 u32 rev_id; /* 0x00 */ 68 u32 status; /* 0x04 */ 69 u32 f_control; /* 0x08 */ 70 u32 reserve_1; /* 0x0C */ 71 u32 vidout_ctrl; /* 0x10 */ 72 u32 sync_ctrl; /* 0x14 */ 73 u32 reserve_2; /* 0x18 */ 74 u32 llen; /* 0x1C */ 75 u32 flens; /* 0x20 */ 76 u32 hfltr_ctrl; /* 0x24 */ 77 u32 cc_carr_wss_carr; /* 0x28 */ 78 u32 c_phase; /* 0x2C */ 79 u32 gain_u; /* 0x30 */ 80 u32 gain_v; /* 0x34 */ 81 u32 gain_y; /* 0x38 */ 82 u32 black_level; /* 0x3C */ 83 u32 blank_level; /* 0x40 */ 84 u32 x_color; /* 0x44 */ 85 u32 m_control; /* 0x48 */ 86 u32 bstamp_wss_data; /* 0x4C */ 87 u32 s_carr; /* 0x50 */ 88 u32 line21; /* 0x54 */ 89 u32 ln_sel; /* 0x58 */ 90 u32 l21__wc_ctl; /* 0x5C */ 91 u32 htrigger_vtrigger; /* 0x60 */ 92 u32 savid__eavid; /* 0x64 */ 93 u32 flen__fal; /* 0x68 */ 94 u32 lal__phase_reset; /* 0x6C */ 95 u32 hs_int_start_stop_x; /* 0x70 */ 96 u32 hs_ext_start_stop_x; /* 0x74 */ 97 u32 vs_int_start_x; /* 0x78 */ 98 u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ 99 u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ 100 u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ 101 u32 vs_ext_stop_y; /* 0x88 */ 102 u32 reserve_3; /* 0x8C */ 103 u32 avid_start_stop_x; /* 0x90 */ 104 u32 avid_start_stop_y; /* 0x94 */ 105 u32 reserve_4; /* 0x98 */ 106 u32 reserve_5; /* 0x9C */ 107 u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ 108 u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ 109 u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ 110 u32 reserve_6; /* 0xAC */ 111 u32 tvdetgp_int_start_stop_x; /* 0xB0 */ 112 u32 tvdetgp_int_start_stop_y; /* 0xB4 */ 113 u32 gen_ctrl; /* 0xB8 */ 114 u32 reserve_7; /* 0xBC */ 115 u32 reserve_8; /* 0xC0 */ 116 u32 output_control; /* 0xC4 */ 117 u32 dac_b__dac_c; /* 0xC8 */ 118 u32 height_width; /* 0xCC */ 119 }; 120 121 /* Few Register Offsets */ 122 #define FRAME_MODE_SHIFT 1 123 #define TFTSTN_SHIFT 3 124 #define DATALINES_SHIFT 8 125 126 /* Enabling Display controller */ 127 #define LCD_ENABLE 1 128 #define DIG_ENABLE (1 << 1) 129 #define GO_LCD (1 << 5) 130 #define GO_DIG (1 << 6) 131 #define GP_OUT0 (1 << 15) 132 #define GP_OUT1 (1 << 16) 133 134 #define DISPC_ENABLE (LCD_ENABLE | \ 135 DIG_ENABLE | \ 136 GO_LCD | \ 137 GO_DIG | \ 138 GP_OUT0| \ 139 GP_OUT1) 140 141 /* Configure VENC DSS Params */ 142 #define VENC_CLK_ENABLE (1 << 3) 143 #define DAC_DEMEN (1 << 4) 144 #define DAC_POWERDN (1 << 5) 145 #define VENC_OUT_SEL (1 << 6) 146 #define DIG_LPP_SHIFT 16 147 #define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \ 148 DAC_DEMEN | \ 149 DAC_POWERDN | \ 150 VENC_OUT_SEL) 151 /* 152 * Panel Configuration 153 */ 154 struct panel_config { 155 u32 timing_h; 156 u32 timing_v; 157 u32 pol_freq; 158 u32 divisor; 159 u32 lcd_size; 160 u32 panel_type; 161 u32 data_lines; 162 u32 load_mode; 163 u32 panel_color; 164 }; 165 166 /* 167 * Generic DSS Functions 168 */ 169 void omap3_dss_venc_config(const struct venc_regs *venc_cfg, 170 u32 height, u32 width); 171 void omap3_dss_panel_config(const struct panel_config *panel_cfg); 172 void omap3_dss_enable(void); 173 174 #endif /* DSS_H */ 175