1*4c4bb19dSSimon Schwarz #ifndef __SDMA_H 2*4c4bb19dSSimon Schwarz #define __SDMA_H 3*4c4bb19dSSimon Schwarz 4*4c4bb19dSSimon Schwarz /* Copyright (C) 2011 5*4c4bb19dSSimon Schwarz * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> 6*4c4bb19dSSimon Schwarz * 7*4c4bb19dSSimon Schwarz * This program is free software; you can redistribute it and/or 8*4c4bb19dSSimon Schwarz * modify it under the terms of the GNU General Public License as 9*4c4bb19dSSimon Schwarz * published by the Free Software Foundation; either version 2 of 10*4c4bb19dSSimon Schwarz * the License, or (at your option) any later version. 11*4c4bb19dSSimon Schwarz * 12*4c4bb19dSSimon Schwarz * This program is distributed in the hope that it will be useful, 13*4c4bb19dSSimon Schwarz * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*4c4bb19dSSimon Schwarz * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*4c4bb19dSSimon Schwarz * GNU General Public License for more details. 16*4c4bb19dSSimon Schwarz * 17*4c4bb19dSSimon Schwarz * You should have received a copy of the GNU General Public License 18*4c4bb19dSSimon Schwarz * along with this program; if not, write to the Free Software 19*4c4bb19dSSimon Schwarz * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*4c4bb19dSSimon Schwarz * MA 02111-1307 USA 21*4c4bb19dSSimon Schwarz */ 22*4c4bb19dSSimon Schwarz 23*4c4bb19dSSimon Schwarz /* Functions */ 24*4c4bb19dSSimon Schwarz void omap3_dma_init(void); 25*4c4bb19dSSimon Schwarz int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, 26*4c4bb19dSSimon Schwarz uint32_t sze); 27*4c4bb19dSSimon Schwarz int omap3_dma_start_transfer(uint32_t chan); 28*4c4bb19dSSimon Schwarz int omap3_dma_wait_for_transfer(uint32_t chan); 29*4c4bb19dSSimon Schwarz int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); 30*4c4bb19dSSimon Schwarz int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); 31*4c4bb19dSSimon Schwarz 32*4c4bb19dSSimon Schwarz /* Register settings */ 33*4c4bb19dSSimon Schwarz #define CSDP_DATA_TYPE_8BIT 0x0 34*4c4bb19dSSimon Schwarz #define CSDP_DATA_TYPE_16BIT 0x1 35*4c4bb19dSSimon Schwarz #define CSDP_DATA_TYPE_32BIT 0x2 36*4c4bb19dSSimon Schwarz #define CSDP_SRC_BURST_SINGLE (0x0 << 7) 37*4c4bb19dSSimon Schwarz #define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) 38*4c4bb19dSSimon Schwarz #define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) 39*4c4bb19dSSimon Schwarz #define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) 40*4c4bb19dSSimon Schwarz #define CSDP_DST_BURST_SINGLE (0x0 << 14) 41*4c4bb19dSSimon Schwarz #define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) 42*4c4bb19dSSimon Schwarz #define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) 43*4c4bb19dSSimon Schwarz #define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) 44*4c4bb19dSSimon Schwarz #define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) 45*4c4bb19dSSimon Schwarz #define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) 46*4c4bb19dSSimon Schwarz #define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) 47*4c4bb19dSSimon Schwarz #define CSDP_DST_ENDIAN_BIG (0x1 << 19) 48*4c4bb19dSSimon Schwarz #define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) 49*4c4bb19dSSimon Schwarz #define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) 50*4c4bb19dSSimon Schwarz #define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) 51*4c4bb19dSSimon Schwarz #define CSDP_SRC_ENDIAN_BIG (0x1 << 21) 52*4c4bb19dSSimon Schwarz 53*4c4bb19dSSimon Schwarz #define CCR_READ_PRIORITY_LOW (0x0 << 6) 54*4c4bb19dSSimon Schwarz #define CCR_READ_PRIORITY_HIGH (0x1 << 6) 55*4c4bb19dSSimon Schwarz #define CCR_ENABLE_DISABLED (0x0 << 7) 56*4c4bb19dSSimon Schwarz #define CCR_ENABLE_ENABLE (0x1 << 7) 57*4c4bb19dSSimon Schwarz #define CCR_SRC_AMODE_CONSTANT (0x0 << 12) 58*4c4bb19dSSimon Schwarz #define CCR_SRC_AMODE_POST_INC (0x1 << 12) 59*4c4bb19dSSimon Schwarz #define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) 60*4c4bb19dSSimon Schwarz #define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) 61*4c4bb19dSSimon Schwarz #define CCR_DST_AMODE_CONSTANT (0x0 << 14) 62*4c4bb19dSSimon Schwarz #define CCR_DST_AMODE_POST_INC (0x1 << 14) 63*4c4bb19dSSimon Schwarz #define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) 64*4c4bb19dSSimon Schwarz #define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) 65*4c4bb19dSSimon Schwarz 66*4c4bb19dSSimon Schwarz #define CCR_RD_ACTIVE_MASK (1 << 9) 67*4c4bb19dSSimon Schwarz #define CCR_WR_ACTIVE_MASK (1 << 10) 68*4c4bb19dSSimon Schwarz 69*4c4bb19dSSimon Schwarz #define CSR_TRANS_ERR (1 << 8) 70*4c4bb19dSSimon Schwarz #define CSR_SUPERVISOR_ERR (1 << 10) 71*4c4bb19dSSimon Schwarz #define CSR_MISALIGNED_ADRS_ERR (1 << 11) 72*4c4bb19dSSimon Schwarz 73*4c4bb19dSSimon Schwarz /* others */ 74*4c4bb19dSSimon Schwarz #define CHAN_NR_MIN 0 75*4c4bb19dSSimon Schwarz #define CHAN_NR_MAX 31 76*4c4bb19dSSimon Schwarz 77*4c4bb19dSSimon Schwarz #endif /* __SDMA_H */ 78