1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CPU_H 9 #define _CPU_H 10 11 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 12 #include <asm/types.h> 13 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 14 15 /* Register offsets of common modules */ 16 /* Control */ 17 #ifndef __KERNEL_STRICT_NAMES 18 #ifndef __ASSEMBLY__ 19 struct ctrl { 20 u8 res1[0xC0]; 21 u16 gpmc_nadv_ale; /* 0xC0 */ 22 u16 gpmc_noe; /* 0xC2 */ 23 u16 gpmc_nwe; /* 0xC4 */ 24 u8 res2[0x22A]; 25 u32 status; /* 0x2F0 */ 26 u32 gpstatus; /* 0x2F4 */ 27 u8 res3[0x08]; 28 u32 rpubkey_0; /* 0x300 */ 29 u32 rpubkey_1; /* 0x304 */ 30 u32 rpubkey_2; /* 0x308 */ 31 u32 rpubkey_3; /* 0x30C */ 32 u32 rpubkey_4; /* 0x310 */ 33 u8 res4[0x04]; 34 u32 randkey_0; /* 0x318 */ 35 u32 randkey_1; /* 0x31C */ 36 u32 randkey_2; /* 0x320 */ 37 u32 randkey_3; /* 0x324 */ 38 u8 res5[0x124]; 39 u32 ctrl_omap_stat; /* 0x44C */ 40 }; 41 #else /* __ASSEMBLY__ */ 42 #define CONTROL_STATUS 0x2F0 43 #endif /* __ASSEMBLY__ */ 44 #endif /* __KERNEL_STRICT_NAMES */ 45 46 #ifndef __KERNEL_STRICT_NAMES 47 #ifndef __ASSEMBLY__ 48 struct ctrl_id { 49 u8 res1[0x4]; 50 u32 idcode; /* 0x04 */ 51 u32 prod_id; /* 0x08 */ 52 u32 sku_id; /* 0x0c */ 53 u8 res2[0x08]; 54 u32 die_id_0; /* 0x18 */ 55 u32 die_id_1; /* 0x1C */ 56 u32 die_id_2; /* 0x20 */ 57 u32 die_id_3; /* 0x24 */ 58 }; 59 #endif /* __ASSEMBLY__ */ 60 #endif /* __KERNEL_STRICT_NAMES */ 61 62 /* device type */ 63 #define DEVICE_MASK (0x7 << 8) 64 #define SYSBOOT_MASK 0x1F 65 #define TST_DEVICE 0x0 66 #define EMU_DEVICE 0x1 67 #define HS_DEVICE 0x2 68 #define GP_DEVICE 0x3 69 70 /* device speed */ 71 #define SKUID_CLK_MASK 0xf 72 #define SKUID_CLK_600MHZ 0x0 73 #define SKUID_CLK_720MHZ 0x8 74 75 #define GPMC_BASE (OMAP34XX_GPMC_BASE) 76 #define GPMC_CONFIG_CS0 0x60 77 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) 78 79 #ifndef __KERNEL_STRICT_NAMES 80 #ifndef __ASSEMBLY__ 81 struct gpmc_cs { 82 u32 config1; /* 0x00 */ 83 u32 config2; /* 0x04 */ 84 u32 config3; /* 0x08 */ 85 u32 config4; /* 0x0C */ 86 u32 config5; /* 0x10 */ 87 u32 config6; /* 0x14 */ 88 u32 config7; /* 0x18 */ 89 u32 nand_cmd; /* 0x1C */ 90 u32 nand_adr; /* 0x20 */ 91 u32 nand_dat; /* 0x24 */ 92 u8 res[8]; /* blow up to 0x30 byte */ 93 }; 94 95 struct bch_res_0_3 { 96 u32 bch_result_x[4]; 97 }; 98 99 struct gpmc { 100 u8 res1[0x10]; 101 u32 sysconfig; /* 0x10 */ 102 u8 res2[0x4]; 103 u32 irqstatus; /* 0x18 */ 104 u32 irqenable; /* 0x1C */ 105 u8 res3[0x20]; 106 u32 timeout_control; /* 0x40 */ 107 u8 res4[0xC]; 108 u32 config; /* 0x50 */ 109 u32 status; /* 0x54 */ 110 u8 res5[0x8]; /* 0x58 */ 111 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 112 u8 res6[0x14]; /* 0x1E0 */ 113 u32 ecc_config; /* 0x1F4 */ 114 u32 ecc_control; /* 0x1F8 */ 115 u32 ecc_size_config; /* 0x1FC */ 116 u32 ecc1_result; /* 0x200 */ 117 u32 ecc2_result; /* 0x204 */ 118 u32 ecc3_result; /* 0x208 */ 119 u32 ecc4_result; /* 0x20C */ 120 u32 ecc5_result; /* 0x210 */ 121 u32 ecc6_result; /* 0x214 */ 122 u32 ecc7_result; /* 0x218 */ 123 u32 ecc8_result; /* 0x21C */ 124 u32 ecc9_result; /* 0x220 */ 125 u8 res7[0x1C]; /* fill up to 0x240 */ 126 struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */ 127 }; 128 129 /* Used for board specific gpmc initialization */ 130 extern struct gpmc *gpmc_cfg; 131 132 #else /* __ASSEMBLY__ */ 133 #define GPMC_CONFIG1 0x00 134 #define GPMC_CONFIG2 0x04 135 #define GPMC_CONFIG3 0x08 136 #define GPMC_CONFIG4 0x0C 137 #define GPMC_CONFIG5 0x10 138 #define GPMC_CONFIG6 0x14 139 #define GPMC_CONFIG7 0x18 140 #endif /* __ASSEMBLY__ */ 141 #endif /* __KERNEL_STRICT_NAMES */ 142 143 /* GPMC Mapping */ 144 #define FLASH_BASE 0x10000000 /* NOR flash, */ 145 /* aligned to 256 Meg */ 146 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ 147 /* aligned to 64 Meg */ 148 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ 149 /* aligned to 256 Meg */ 150 #define DEBUG_BASE 0x08000000 /* debug board */ 151 #define NAND_BASE 0x30000000 /* NAND addr */ 152 /* (actual size small port) */ 153 #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ 154 #define ONENAND_MAP 0x20000000 /* OneNand addr */ 155 /* (actual size small port) */ 156 /* SMS */ 157 #ifndef __KERNEL_STRICT_NAMES 158 #ifndef __ASSEMBLY__ 159 struct sms { 160 u8 res1[0x10]; 161 u32 sysconfig; /* 0x10 */ 162 u8 res2[0x34]; 163 u32 rg_att0; /* 0x48 */ 164 u8 res3[0x84]; 165 u32 class_arb0; /* 0xD0 */ 166 }; 167 #endif /* __ASSEMBLY__ */ 168 #endif /* __KERNEL_STRICT_NAMES */ 169 170 #define BURSTCOMPLETE_GROUP7 (0x1 << 31) 171 172 /* SDRC */ 173 #ifndef __KERNEL_STRICT_NAMES 174 #ifndef __ASSEMBLY__ 175 struct sdrc_cs { 176 u32 mcfg; /* 0x80 || 0xB0 */ 177 u32 mr; /* 0x84 || 0xB4 */ 178 u8 res1[0x4]; 179 u32 emr2; /* 0x8C || 0xBC */ 180 u8 res2[0x14]; 181 u32 rfr_ctrl; /* 0x84 || 0xD4 */ 182 u32 manual; /* 0xA8 || 0xD8 */ 183 u8 res3[0x4]; 184 }; 185 186 struct sdrc_actim { 187 u32 ctrla; /* 0x9C || 0xC4 */ 188 u32 ctrlb; /* 0xA0 || 0xC8 */ 189 }; 190 191 struct sdrc { 192 u8 res1[0x10]; 193 u32 sysconfig; /* 0x10 */ 194 u32 status; /* 0x14 */ 195 u8 res2[0x28]; 196 u32 cs_cfg; /* 0x40 */ 197 u32 sharing; /* 0x44 */ 198 u8 res3[0x18]; 199 u32 dlla_ctrl; /* 0x60 */ 200 u32 dlla_status; /* 0x64 */ 201 u32 dllb_ctrl; /* 0x68 */ 202 u32 dllb_status; /* 0x6C */ 203 u32 power; /* 0x70 */ 204 u8 res4[0xC]; 205 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ 206 }; 207 208 /* EMIF4 */ 209 typedef struct emif4 { 210 unsigned int emif_mod_id_rev; 211 unsigned int sdram_sts; 212 unsigned int sdram_config; 213 unsigned int res1; 214 unsigned int sdram_refresh_ctrl; 215 unsigned int sdram_refresh_ctrl_shdw; 216 unsigned int sdram_time1; 217 unsigned int sdram_time1_shdw; 218 unsigned int sdram_time2; 219 unsigned int sdram_time2_shdw; 220 unsigned int sdram_time3; 221 unsigned int sdram_time3_shdw; 222 unsigned char res2[8]; 223 unsigned int sdram_pwr_mgmt; 224 unsigned int sdram_pwr_mgmt_shdw; 225 unsigned char res3[32]; 226 unsigned int sdram_iodft_tlgc; 227 unsigned char res4[128]; 228 unsigned int ddr_phyctrl1; 229 unsigned int ddr_phyctrl1_shdw; 230 unsigned int ddr_phyctrl2; 231 } emif4_t; 232 233 #endif /* __ASSEMBLY__ */ 234 #endif /* __KERNEL_STRICT_NAMES */ 235 236 #define DLLPHASE_90 (0x1 << 1) 237 #define LOADDLL (0x1 << 2) 238 #define ENADLL (0x1 << 3) 239 #define DLL_DELAY_MASK 0xFF00 240 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) 241 242 #define PAGEPOLICY_HIGH (0x1 << 0) 243 #define SRFRONRESET (0x1 << 7) 244 #define PWDNEN (0x1 << 2) 245 #define WAKEUPPROC (0x1 << 26) 246 247 #define DDR_SDRAM (0x1 << 0) 248 #define DEEPPD (0x1 << 3) 249 #define B32NOT16 (0x1 << 4) 250 #define BANKALLOCATION (0x2 << 6) 251 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ 252 #define ADDRMUXLEGACY (0x1 << 19) 253 #define CASWIDTH_10BITS (0x5 << 20) 254 #define RASWIDTH_13BITS (0x2 << 24) 255 #define BURSTLENGTH4 (0x2 << 0) 256 #define CASL3 (0x3 << 4) 257 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) 258 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) 259 #define ARE_ARCV_1 (0x1 << 0) 260 #define ARCV (0x4e2 << 8) /* Autorefresh count */ 261 #define OMAP34XX_SDRC_CS0 0x80000000 262 #define OMAP34XX_SDRC_CS1 0xA0000000 263 #define CMD_NOP 0x0 264 #define CMD_PRECHARGE 0x1 265 #define CMD_AUTOREFRESH 0x2 266 #define CMD_ENTR_PWRDOWN 0x3 267 #define CMD_EXIT_PWRDOWN 0x4 268 #define CMD_ENTR_SRFRSH 0x5 269 #define CMD_CKE_HIGH 0x6 270 #define CMD_CKE_LOW 0x7 271 #define SOFTRESET (0x1 << 1) 272 #define SMART_IDLE (0x2 << 3) 273 #define REF_ON_IDLE (0x1 << 6) 274 275 /* DMA */ 276 #ifndef __KERNEL_STRICT_NAMES 277 #ifndef __ASSEMBLY__ 278 struct dma4_chan { 279 u32 ccr; 280 u32 clnk_ctrl; 281 u32 cicr; 282 u32 csr; 283 u32 csdp; 284 u32 cen; 285 u32 cfn; 286 u32 cssa; 287 u32 cdsa; 288 u32 csel; 289 u32 csfl; 290 u32 cdel; 291 u32 cdfl; 292 u32 csac; 293 u32 cdac; 294 u32 ccen; 295 u32 ccfn; 296 u32 color; 297 }; 298 299 struct dma4 { 300 u32 revision; 301 u8 res1[0x4]; 302 u32 irqstatus_l[0x4]; 303 u32 irqenable_l[0x4]; 304 u32 sysstatus; 305 u32 ocp_sysconfig; 306 u8 res2[0x34]; 307 u32 caps_0; 308 u8 res3[0x4]; 309 u32 caps_2; 310 u32 caps_3; 311 u32 caps_4; 312 u32 gcr; 313 u8 res4[0x4]; 314 struct dma4_chan chan[32]; 315 }; 316 317 #endif /*__ASSEMBLY__ */ 318 #endif /* __KERNEL_STRICT_NAMES */ 319 320 /* timer regs offsets (32 bit regs) */ 321 322 #ifndef __KERNEL_STRICT_NAMES 323 #ifndef __ASSEMBLY__ 324 struct gptimer { 325 u32 tidr; /* 0x00 r */ 326 u8 res[0xc]; 327 u32 tiocp_cfg; /* 0x10 rw */ 328 u32 tistat; /* 0x14 r */ 329 u32 tisr; /* 0x18 rw */ 330 u32 tier; /* 0x1c rw */ 331 u32 twer; /* 0x20 rw */ 332 u32 tclr; /* 0x24 rw */ 333 u32 tcrr; /* 0x28 rw */ 334 u32 tldr; /* 0x2c rw */ 335 u32 ttgr; /* 0x30 rw */ 336 u32 twpc; /* 0x34 r*/ 337 u32 tmar; /* 0x38 rw*/ 338 u32 tcar1; /* 0x3c r */ 339 u32 tcicr; /* 0x40 rw */ 340 u32 tcar2; /* 0x44 r */ 341 }; 342 #endif /* __ASSEMBLY__ */ 343 #endif /* __KERNEL_STRICT_NAMES */ 344 345 /* enable sys_clk NO-prescale /1 */ 346 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 347 348 /* Watchdog */ 349 #ifndef __KERNEL_STRICT_NAMES 350 #ifndef __ASSEMBLY__ 351 struct watchdog { 352 u8 res1[0x34]; 353 u32 wwps; /* 0x34 r */ 354 u8 res2[0x10]; 355 u32 wspr; /* 0x48 rw */ 356 }; 357 #endif /* __ASSEMBLY__ */ 358 #endif /* __KERNEL_STRICT_NAMES */ 359 360 #define WD_UNLOCK1 0xAAAA 361 #define WD_UNLOCK2 0x5555 362 363 /* PRCM */ 364 #define PRCM_BASE 0x48004000 365 366 #ifndef __KERNEL_STRICT_NAMES 367 #ifndef __ASSEMBLY__ 368 struct prcm { 369 u32 fclken_iva2; /* 0x00 */ 370 u32 clken_pll_iva2; /* 0x04 */ 371 u8 res1[0x1c]; 372 u32 idlest_pll_iva2; /* 0x24 */ 373 u8 res2[0x18]; 374 u32 clksel1_pll_iva2 ; /* 0x40 */ 375 u32 clksel2_pll_iva2; /* 0x44 */ 376 u8 res3[0x8bc]; 377 u32 clken_pll_mpu; /* 0x904 */ 378 u8 res4[0x1c]; 379 u32 idlest_pll_mpu; /* 0x924 */ 380 u8 res5[0x18]; 381 u32 clksel1_pll_mpu; /* 0x940 */ 382 u32 clksel2_pll_mpu; /* 0x944 */ 383 u8 res6[0xb8]; 384 u32 fclken1_core; /* 0xa00 */ 385 u32 res_fclken2_core; 386 u32 fclken3_core; /* 0xa08 */ 387 u8 res7[0x4]; 388 u32 iclken1_core; /* 0xa10 */ 389 u32 iclken2_core; /* 0xa14 */ 390 u32 iclken3_core; /* 0xa18 */ 391 u8 res8[0x24]; 392 u32 clksel_core; /* 0xa40 */ 393 u8 res9[0xbc]; 394 u32 fclken_gfx; /* 0xb00 */ 395 u8 res10[0xc]; 396 u32 iclken_gfx; /* 0xb10 */ 397 u8 res11[0x2c]; 398 u32 clksel_gfx; /* 0xb40 */ 399 u8 res12[0xbc]; 400 u32 fclken_wkup; /* 0xc00 */ 401 u8 res13[0xc]; 402 u32 iclken_wkup; /* 0xc10 */ 403 u8 res14[0xc]; 404 u32 idlest_wkup; /* 0xc20 */ 405 u8 res15[0x1c]; 406 u32 clksel_wkup; /* 0xc40 */ 407 u8 res16[0xbc]; 408 u32 clken_pll; /* 0xd00 */ 409 u32 clken2_pll; /* 0xd04 */ 410 u8 res17[0x18]; 411 u32 idlest_ckgen; /* 0xd20 */ 412 u32 idlest2_ckgen; /* 0xd24 */ 413 u8 res18[0x18]; 414 u32 clksel1_pll; /* 0xd40 */ 415 u32 clksel2_pll; /* 0xd44 */ 416 u32 clksel3_pll; /* 0xd48 */ 417 u32 clksel4_pll; /* 0xd4c */ 418 u32 clksel5_pll; /* 0xd50 */ 419 u8 res19[0xac]; 420 u32 fclken_dss; /* 0xe00 */ 421 u8 res20[0xc]; 422 u32 iclken_dss; /* 0xe10 */ 423 u8 res21[0x2c]; 424 u32 clksel_dss; /* 0xe40 */ 425 u8 res22[0xbc]; 426 u32 fclken_cam; /* 0xf00 */ 427 u8 res23[0xc]; 428 u32 iclken_cam; /* 0xf10 */ 429 u8 res24[0x2c]; 430 u32 clksel_cam; /* 0xf40 */ 431 u8 res25[0xbc]; 432 u32 fclken_per; /* 0x1000 */ 433 u8 res26[0xc]; 434 u32 iclken_per; /* 0x1010 */ 435 u8 res27[0x2c]; 436 u32 clksel_per; /* 0x1040 */ 437 u8 res28[0xfc]; 438 u32 clksel1_emu; /* 0x1140 */ 439 u8 res29[0x2bc]; 440 u32 fclken_usbhost; /* 0x1400 */ 441 u8 res30[0xc]; 442 u32 iclken_usbhost; /* 0x1410 */ 443 }; 444 #else /* __ASSEMBLY__ */ 445 #define CM_CLKSEL_CORE 0x48004a40 446 #define CM_CLKSEL_GFX 0x48004b40 447 #define CM_CLKSEL_WKUP 0x48004c40 448 #define CM_CLKEN_PLL 0x48004d00 449 #define CM_CLKSEL1_PLL 0x48004d40 450 #define CM_CLKSEL1_EMU 0x48005140 451 #endif /* __ASSEMBLY__ */ 452 #endif /* __KERNEL_STRICT_NAMES */ 453 454 #define PRM_BASE 0x48306000 455 456 #ifndef __KERNEL_STRICT_NAMES 457 #ifndef __ASSEMBLY__ 458 struct prm { 459 u8 res1[0xd40]; 460 u32 clksel; /* 0xd40 */ 461 u8 res2[0x50c]; 462 u32 rstctrl; /* 0x1250 */ 463 u8 res3[0x1c]; 464 u32 clksrc_ctrl; /* 0x1270 */ 465 }; 466 #endif /* __ASSEMBLY__ */ 467 #endif /* __KERNEL_STRICT_NAMES */ 468 469 #define PRM_RSTCTRL 0x48307250 470 #define PRM_RSTCTRL_RESET 0x04 471 #define PRM_RSTST 0x48307258 472 #define PRM_RSTST_WARM_RESET_MASK 0x7D2 473 #define SYSCLKDIV_1 (0x1 << 6) 474 #define SYSCLKDIV_2 (0x1 << 7) 475 476 #define CLKSEL_GPT1 (0x1 << 0) 477 478 #define EN_GPT1 (0x1 << 0) 479 #define EN_32KSYNC (0x1 << 2) 480 481 #define ST_WDT2 (0x1 << 5) 482 483 #define ST_MPU_CLK (0x1 << 0) 484 485 #define ST_CORE_CLK (0x1 << 0) 486 487 #define ST_PERIPH_CLK (0x1 << 1) 488 489 #define ST_IVA2_CLK (0x1 << 0) 490 491 #define RESETDONE (0x1 << 0) 492 493 #define TCLR_ST (0x1 << 0) 494 #define TCLR_AR (0x1 << 1) 495 #define TCLR_PRE (0x1 << 5) 496 497 /* SMX-APE */ 498 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 499 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 500 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 501 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 502 503 #ifndef __KERNEL_STRICT_NAMES 504 #ifndef __ASSEMBLY__ 505 struct pm { 506 u8 res1[0x48]; 507 u32 req_info_permission_0; /* 0x48 */ 508 u8 res2[0x4]; 509 u32 read_permission_0; /* 0x50 */ 510 u8 res3[0x4]; 511 u32 wirte_permission_0; /* 0x58 */ 512 u8 res4[0x4]; 513 u32 addr_match_1; /* 0x58 */ 514 u8 res5[0x4]; 515 u32 req_info_permission_1; /* 0x68 */ 516 u8 res6[0x14]; 517 u32 addr_match_2; /* 0x80 */ 518 }; 519 #endif /*__ASSEMBLY__ */ 520 #endif /* __KERNEL_STRICT_NAMES */ 521 522 /* Permission values for registers -Full fledged permissions to all */ 523 #define UNLOCK_1 0xFFFFFFFF 524 #define UNLOCK_2 0x00000000 525 #define UNLOCK_3 0x0000FFFF 526 527 #define NOT_EARLY 0 528 529 /* I2C base */ 530 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) 531 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) 532 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) 533 534 /* MUSB base */ 535 #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) 536 537 /* OMAP3 GPIO registers */ 538 #define OMAP_GPIO_REVISION 0x0000 539 #define OMAP_GPIO_SYSCONFIG 0x0010 540 #define OMAP_GPIO_SYSSTATUS 0x0014 541 #define OMAP_GPIO_IRQSTATUS1 0x0018 542 #define OMAP_GPIO_IRQSTATUS2 0x0028 543 #define OMAP_GPIO_IRQENABLE2 0x002c 544 #define OMAP_GPIO_IRQENABLE1 0x001c 545 #define OMAP_GPIO_WAKE_EN 0x0020 546 #define OMAP_GPIO_CTRL 0x0030 547 #define OMAP_GPIO_OE 0x0034 548 #define OMAP_GPIO_DATAIN 0x0038 549 #define OMAP_GPIO_DATAOUT 0x003c 550 #define OMAP_GPIO_LEVELDETECT0 0x0040 551 #define OMAP_GPIO_LEVELDETECT1 0x0044 552 #define OMAP_GPIO_RISINGDETECT 0x0048 553 #define OMAP_GPIO_FALLINGDETECT 0x004c 554 #define OMAP_GPIO_DEBOUNCE_EN 0x0050 555 #define OMAP_GPIO_DEBOUNCE_VAL 0x0054 556 #define OMAP_GPIO_CLEARIRQENABLE1 0x0060 557 #define OMAP_GPIO_SETIRQENABLE1 0x0064 558 #define OMAP_GPIO_CLEARWKUENA 0x0080 559 #define OMAP_GPIO_SETWKUENA 0x0084 560 #define OMAP_GPIO_CLEARDATAOUT 0x0090 561 #define OMAP_GPIO_SETDATAOUT 0x0094 562 563 #endif /* _CPU_H */ 564