1819833afSPeter Tyser /* 2819833afSPeter Tyser * (C) Copyright 2006-2008 3819833afSPeter Tyser * Texas Instruments, <www.ti.com> 4819833afSPeter Tyser * 5819833afSPeter Tyser * See file CREDITS for list of people who contributed to this 6819833afSPeter Tyser * project. 7819833afSPeter Tyser * 8819833afSPeter Tyser * This program is free software; you can redistribute it and/or 9819833afSPeter Tyser * modify it under the terms of the GNU General Public License as 10819833afSPeter Tyser * published by the Free Software Foundation; either version 2 of 11819833afSPeter Tyser * the License, or (at your option) any later version. 12819833afSPeter Tyser * 13819833afSPeter Tyser * This program is distributed in the hope that it will be useful, 14819833afSPeter Tyser * but WITHOUT ANY WARRANTY; without even the implied warranty of 15819833afSPeter Tyser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16819833afSPeter Tyser * GNU General Public License for more details. 17819833afSPeter Tyser * 18819833afSPeter Tyser * You should have received a copy of the GNU General Public License 19819833afSPeter Tyser * along with this program; if not, write to the Free Software 20819833afSPeter Tyser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21819833afSPeter Tyser * MA 02111-1307 USA 22819833afSPeter Tyser * 23819833afSPeter Tyser */ 24819833afSPeter Tyser 25819833afSPeter Tyser #ifndef _CPU_H 26819833afSPeter Tyser #define _CPU_H 27819833afSPeter Tyser 28819833afSPeter Tyser #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 29819833afSPeter Tyser #include <asm/types.h> 30819833afSPeter Tyser #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 31819833afSPeter Tyser 32819833afSPeter Tyser /* Register offsets of common modules */ 33819833afSPeter Tyser /* Control */ 34819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 35819833afSPeter Tyser #ifndef __ASSEMBLY__ 36819833afSPeter Tyser struct ctrl { 37819833afSPeter Tyser u8 res1[0xC0]; 38819833afSPeter Tyser u16 gpmc_nadv_ale; /* 0xC0 */ 39819833afSPeter Tyser u16 gpmc_noe; /* 0xC2 */ 40819833afSPeter Tyser u16 gpmc_nwe; /* 0xC4 */ 41819833afSPeter Tyser u8 res2[0x22A]; 42819833afSPeter Tyser u32 status; /* 0x2F0 */ 43819833afSPeter Tyser u32 gpstatus; /* 0x2F4 */ 44819833afSPeter Tyser u8 res3[0x08]; 45819833afSPeter Tyser u32 rpubkey_0; /* 0x300 */ 46819833afSPeter Tyser u32 rpubkey_1; /* 0x304 */ 47819833afSPeter Tyser u32 rpubkey_2; /* 0x308 */ 48819833afSPeter Tyser u32 rpubkey_3; /* 0x30C */ 49819833afSPeter Tyser u32 rpubkey_4; /* 0x310 */ 50819833afSPeter Tyser u8 res4[0x04]; 51819833afSPeter Tyser u32 randkey_0; /* 0x318 */ 52819833afSPeter Tyser u32 randkey_1; /* 0x31C */ 53819833afSPeter Tyser u32 randkey_2; /* 0x320 */ 54819833afSPeter Tyser u32 randkey_3; /* 0x324 */ 55819833afSPeter Tyser u8 res5[0x124]; 56819833afSPeter Tyser u32 ctrl_omap_stat; /* 0x44C */ 57819833afSPeter Tyser }; 58819833afSPeter Tyser #else /* __ASSEMBLY__ */ 59819833afSPeter Tyser #define CONTROL_STATUS 0x2F0 60819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 61819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 62819833afSPeter Tyser 63819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 64819833afSPeter Tyser #ifndef __ASSEMBLY__ 65819833afSPeter Tyser struct ctrl_id { 66819833afSPeter Tyser u8 res1[0x4]; 67819833afSPeter Tyser u32 idcode; /* 0x04 */ 68819833afSPeter Tyser u32 prod_id; /* 0x08 */ 69b2b9169fSSteve Sakoman u32 sku_id; /* 0x0c */ 70b2b9169fSSteve Sakoman u8 res2[0x08]; 71819833afSPeter Tyser u32 die_id_0; /* 0x18 */ 72819833afSPeter Tyser u32 die_id_1; /* 0x1C */ 73819833afSPeter Tyser u32 die_id_2; /* 0x20 */ 74819833afSPeter Tyser u32 die_id_3; /* 0x24 */ 75819833afSPeter Tyser }; 76819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 77819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 78819833afSPeter Tyser 79819833afSPeter Tyser /* device type */ 80819833afSPeter Tyser #define DEVICE_MASK (0x7 << 8) 81819833afSPeter Tyser #define SYSBOOT_MASK 0x1F 82819833afSPeter Tyser #define TST_DEVICE 0x0 83819833afSPeter Tyser #define EMU_DEVICE 0x1 84819833afSPeter Tyser #define HS_DEVICE 0x2 85819833afSPeter Tyser #define GP_DEVICE 0x3 86819833afSPeter Tyser 87b2b9169fSSteve Sakoman /* device speed */ 88b2b9169fSSteve Sakoman #define SKUID_CLK_MASK 0xf 89b2b9169fSSteve Sakoman #define SKUID_CLK_600MHZ 0x0 90b2b9169fSSteve Sakoman #define SKUID_CLK_720MHZ 0x8 91b2b9169fSSteve Sakoman 92819833afSPeter Tyser #define GPMC_BASE (OMAP34XX_GPMC_BASE) 93819833afSPeter Tyser #define GPMC_CONFIG_CS0 0x60 94819833afSPeter Tyser #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) 95819833afSPeter Tyser 96819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 97819833afSPeter Tyser #ifndef __ASSEMBLY__ 98819833afSPeter Tyser struct gpmc_cs { 99819833afSPeter Tyser u32 config1; /* 0x00 */ 100819833afSPeter Tyser u32 config2; /* 0x04 */ 101819833afSPeter Tyser u32 config3; /* 0x08 */ 102819833afSPeter Tyser u32 config4; /* 0x0C */ 103819833afSPeter Tyser u32 config5; /* 0x10 */ 104819833afSPeter Tyser u32 config6; /* 0x14 */ 105819833afSPeter Tyser u32 config7; /* 0x18 */ 106819833afSPeter Tyser u32 nand_cmd; /* 0x1C */ 107819833afSPeter Tyser u32 nand_adr; /* 0x20 */ 108819833afSPeter Tyser u32 nand_dat; /* 0x24 */ 109819833afSPeter Tyser u8 res[8]; /* blow up to 0x30 byte */ 110819833afSPeter Tyser }; 111819833afSPeter Tyser 112819833afSPeter Tyser struct gpmc { 113819833afSPeter Tyser u8 res1[0x10]; 114819833afSPeter Tyser u32 sysconfig; /* 0x10 */ 115819833afSPeter Tyser u8 res2[0x4]; 116819833afSPeter Tyser u32 irqstatus; /* 0x18 */ 117819833afSPeter Tyser u32 irqenable; /* 0x1C */ 118819833afSPeter Tyser u8 res3[0x20]; 119819833afSPeter Tyser u32 timeout_control; /* 0x40 */ 120819833afSPeter Tyser u8 res4[0xC]; 121819833afSPeter Tyser u32 config; /* 0x50 */ 122819833afSPeter Tyser u32 status; /* 0x54 */ 123819833afSPeter Tyser u8 res5[0x8]; /* 0x58 */ 124819833afSPeter Tyser struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 125819833afSPeter Tyser u8 res6[0x14]; /* 0x1E0 */ 126819833afSPeter Tyser u32 ecc_config; /* 0x1F4 */ 127819833afSPeter Tyser u32 ecc_control; /* 0x1F8 */ 128819833afSPeter Tyser u32 ecc_size_config; /* 0x1FC */ 129819833afSPeter Tyser u32 ecc1_result; /* 0x200 */ 130819833afSPeter Tyser u32 ecc2_result; /* 0x204 */ 131819833afSPeter Tyser u32 ecc3_result; /* 0x208 */ 132819833afSPeter Tyser u32 ecc4_result; /* 0x20C */ 133819833afSPeter Tyser u32 ecc5_result; /* 0x210 */ 134819833afSPeter Tyser u32 ecc6_result; /* 0x214 */ 135819833afSPeter Tyser u32 ecc7_result; /* 0x218 */ 136819833afSPeter Tyser u32 ecc8_result; /* 0x21C */ 137819833afSPeter Tyser u32 ecc9_result; /* 0x220 */ 138819833afSPeter Tyser }; 139819833afSPeter Tyser 140819833afSPeter Tyser /* Used for board specific gpmc initialization */ 141819833afSPeter Tyser extern struct gpmc *gpmc_cfg; 142819833afSPeter Tyser 143819833afSPeter Tyser #else /* __ASSEMBLY__ */ 144819833afSPeter Tyser #define GPMC_CONFIG1 0x00 145819833afSPeter Tyser #define GPMC_CONFIG2 0x04 146819833afSPeter Tyser #define GPMC_CONFIG3 0x08 147819833afSPeter Tyser #define GPMC_CONFIG4 0x0C 148819833afSPeter Tyser #define GPMC_CONFIG5 0x10 149819833afSPeter Tyser #define GPMC_CONFIG6 0x14 150819833afSPeter Tyser #define GPMC_CONFIG7 0x18 151819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 152819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 153819833afSPeter Tyser 154819833afSPeter Tyser /* GPMC Mapping */ 155819833afSPeter Tyser #define FLASH_BASE 0x10000000 /* NOR flash, */ 156819833afSPeter Tyser /* aligned to 256 Meg */ 157819833afSPeter Tyser #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ 158819833afSPeter Tyser /* aligned to 64 Meg */ 159819833afSPeter Tyser #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ 160819833afSPeter Tyser /* aligned to 256 Meg */ 161819833afSPeter Tyser #define DEBUG_BASE 0x08000000 /* debug board */ 162819833afSPeter Tyser #define NAND_BASE 0x30000000 /* NAND addr */ 163819833afSPeter Tyser /* (actual size small port) */ 164819833afSPeter Tyser #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ 165819833afSPeter Tyser #define ONENAND_MAP 0x20000000 /* OneNand addr */ 166819833afSPeter Tyser /* (actual size small port) */ 167819833afSPeter Tyser /* SMS */ 168819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 169819833afSPeter Tyser #ifndef __ASSEMBLY__ 170819833afSPeter Tyser struct sms { 171819833afSPeter Tyser u8 res1[0x10]; 172819833afSPeter Tyser u32 sysconfig; /* 0x10 */ 173819833afSPeter Tyser u8 res2[0x34]; 174819833afSPeter Tyser u32 rg_att0; /* 0x48 */ 175819833afSPeter Tyser u8 res3[0x84]; 176819833afSPeter Tyser u32 class_arb0; /* 0xD0 */ 177819833afSPeter Tyser }; 178819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 179819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 180819833afSPeter Tyser 181819833afSPeter Tyser #define BURSTCOMPLETE_GROUP7 (0x1 << 31) 182819833afSPeter Tyser 183819833afSPeter Tyser /* SDRC */ 184819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 185819833afSPeter Tyser #ifndef __ASSEMBLY__ 186819833afSPeter Tyser struct sdrc_cs { 187819833afSPeter Tyser u32 mcfg; /* 0x80 || 0xB0 */ 188819833afSPeter Tyser u32 mr; /* 0x84 || 0xB4 */ 189819833afSPeter Tyser u8 res1[0x4]; 190819833afSPeter Tyser u32 emr2; /* 0x8C || 0xBC */ 191819833afSPeter Tyser u8 res2[0x14]; 192819833afSPeter Tyser u32 rfr_ctrl; /* 0x84 || 0xD4 */ 193819833afSPeter Tyser u32 manual; /* 0xA8 || 0xD8 */ 194819833afSPeter Tyser u8 res3[0x4]; 195819833afSPeter Tyser }; 196819833afSPeter Tyser 197819833afSPeter Tyser struct sdrc_actim { 198819833afSPeter Tyser u32 ctrla; /* 0x9C || 0xC4 */ 199819833afSPeter Tyser u32 ctrlb; /* 0xA0 || 0xC8 */ 200819833afSPeter Tyser }; 201819833afSPeter Tyser 202819833afSPeter Tyser struct sdrc { 203819833afSPeter Tyser u8 res1[0x10]; 204819833afSPeter Tyser u32 sysconfig; /* 0x10 */ 205819833afSPeter Tyser u32 status; /* 0x14 */ 206819833afSPeter Tyser u8 res2[0x28]; 207819833afSPeter Tyser u32 cs_cfg; /* 0x40 */ 208819833afSPeter Tyser u32 sharing; /* 0x44 */ 209819833afSPeter Tyser u8 res3[0x18]; 210819833afSPeter Tyser u32 dlla_ctrl; /* 0x60 */ 211819833afSPeter Tyser u32 dlla_status; /* 0x64 */ 212819833afSPeter Tyser u32 dllb_ctrl; /* 0x68 */ 213819833afSPeter Tyser u32 dllb_status; /* 0x6C */ 214819833afSPeter Tyser u32 power; /* 0x70 */ 215819833afSPeter Tyser u8 res4[0xC]; 216819833afSPeter Tyser struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ 217819833afSPeter Tyser }; 218cae377b5SVaibhav Hiremath 2191a5038caSVaibhav Hiremath /* EMIF4 */ 2201a5038caSVaibhav Hiremath typedef struct emif4 { 22140b95c89SIlya Yanok unsigned int emif_mod_id_rev; 2221a5038caSVaibhav Hiremath unsigned int sdram_sts; 2231a5038caSVaibhav Hiremath unsigned int sdram_config; 2241a5038caSVaibhav Hiremath unsigned int res1; 2251a5038caSVaibhav Hiremath unsigned int sdram_refresh_ctrl; 2261a5038caSVaibhav Hiremath unsigned int sdram_refresh_ctrl_shdw; 2271a5038caSVaibhav Hiremath unsigned int sdram_time1; 2281a5038caSVaibhav Hiremath unsigned int sdram_time1_shdw; 2291a5038caSVaibhav Hiremath unsigned int sdram_time2; 2301a5038caSVaibhav Hiremath unsigned int sdram_time2_shdw; 2311a5038caSVaibhav Hiremath unsigned int sdram_time3; 2321a5038caSVaibhav Hiremath unsigned int sdram_time3_shdw; 2331a5038caSVaibhav Hiremath unsigned char res2[8]; 2341a5038caSVaibhav Hiremath unsigned int sdram_pwr_mgmt; 2351a5038caSVaibhav Hiremath unsigned int sdram_pwr_mgmt_shdw; 2361a5038caSVaibhav Hiremath unsigned char res3[32]; 2371a5038caSVaibhav Hiremath unsigned int sdram_iodft_tlgc; 2381a5038caSVaibhav Hiremath unsigned char res4[128]; 2391a5038caSVaibhav Hiremath unsigned int ddr_phyctrl1; 2401a5038caSVaibhav Hiremath unsigned int ddr_phyctrl1_shdw; 2411a5038caSVaibhav Hiremath unsigned int ddr_phyctrl2; 2421a5038caSVaibhav Hiremath } emif4_t; 2431a5038caSVaibhav Hiremath 244819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 245819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 246819833afSPeter Tyser 247819833afSPeter Tyser #define DLLPHASE_90 (0x1 << 1) 248819833afSPeter Tyser #define LOADDLL (0x1 << 2) 249819833afSPeter Tyser #define ENADLL (0x1 << 3) 250819833afSPeter Tyser #define DLL_DELAY_MASK 0xFF00 251819833afSPeter Tyser #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) 252819833afSPeter Tyser 253819833afSPeter Tyser #define PAGEPOLICY_HIGH (0x1 << 0) 254819833afSPeter Tyser #define SRFRONRESET (0x1 << 7) 255819833afSPeter Tyser #define PWDNEN (0x1 << 2) 256819833afSPeter Tyser #define WAKEUPPROC (0x1 << 26) 257819833afSPeter Tyser 258819833afSPeter Tyser #define DDR_SDRAM (0x1 << 0) 259819833afSPeter Tyser #define DEEPPD (0x1 << 3) 260819833afSPeter Tyser #define B32NOT16 (0x1 << 4) 261819833afSPeter Tyser #define BANKALLOCATION (0x2 << 6) 262819833afSPeter Tyser #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ 263819833afSPeter Tyser #define ADDRMUXLEGACY (0x1 << 19) 264819833afSPeter Tyser #define CASWIDTH_10BITS (0x5 << 20) 265819833afSPeter Tyser #define RASWIDTH_13BITS (0x2 << 24) 266819833afSPeter Tyser #define BURSTLENGTH4 (0x2 << 0) 267819833afSPeter Tyser #define CASL3 (0x3 << 4) 268819833afSPeter Tyser #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) 269819833afSPeter Tyser #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) 270819833afSPeter Tyser #define ARE_ARCV_1 (0x1 << 0) 271819833afSPeter Tyser #define ARCV (0x4e2 << 8) /* Autorefresh count */ 272819833afSPeter Tyser #define OMAP34XX_SDRC_CS0 0x80000000 273819833afSPeter Tyser #define OMAP34XX_SDRC_CS1 0xA0000000 274819833afSPeter Tyser #define CMD_NOP 0x0 275819833afSPeter Tyser #define CMD_PRECHARGE 0x1 276819833afSPeter Tyser #define CMD_AUTOREFRESH 0x2 277819833afSPeter Tyser #define CMD_ENTR_PWRDOWN 0x3 278819833afSPeter Tyser #define CMD_EXIT_PWRDOWN 0x4 279819833afSPeter Tyser #define CMD_ENTR_SRFRSH 0x5 280819833afSPeter Tyser #define CMD_CKE_HIGH 0x6 281819833afSPeter Tyser #define CMD_CKE_LOW 0x7 282819833afSPeter Tyser #define SOFTRESET (0x1 << 1) 283819833afSPeter Tyser #define SMART_IDLE (0x2 << 3) 284819833afSPeter Tyser #define REF_ON_IDLE (0x1 << 6) 285819833afSPeter Tyser 2867b646a6dSSimon Schwarz /* DMA */ 2877b646a6dSSimon Schwarz #ifndef __KERNEL_STRICT_NAMES 2887b646a6dSSimon Schwarz #ifndef __ASSEMBLY__ 2897b646a6dSSimon Schwarz struct dma4_chan { 2907b646a6dSSimon Schwarz u32 ccr; 2917b646a6dSSimon Schwarz u32 clnk_ctrl; 2927b646a6dSSimon Schwarz u32 cicr; 2937b646a6dSSimon Schwarz u32 csr; 2947b646a6dSSimon Schwarz u32 csdp; 2957b646a6dSSimon Schwarz u32 cen; 2967b646a6dSSimon Schwarz u32 cfn; 2977b646a6dSSimon Schwarz u32 cssa; 2987b646a6dSSimon Schwarz u32 cdsa; 2997b646a6dSSimon Schwarz u32 csel; 3007b646a6dSSimon Schwarz u32 csfl; 3017b646a6dSSimon Schwarz u32 cdel; 3027b646a6dSSimon Schwarz u32 cdfl; 3037b646a6dSSimon Schwarz u32 csac; 3047b646a6dSSimon Schwarz u32 cdac; 3057b646a6dSSimon Schwarz u32 ccen; 3067b646a6dSSimon Schwarz u32 ccfn; 3077b646a6dSSimon Schwarz u32 color; 3087b646a6dSSimon Schwarz }; 3097b646a6dSSimon Schwarz 3107b646a6dSSimon Schwarz struct dma4 { 3117b646a6dSSimon Schwarz u32 revision; 3127b646a6dSSimon Schwarz u8 res1[0x4]; 3137b646a6dSSimon Schwarz u32 irqstatus_l[0x4]; 3147b646a6dSSimon Schwarz u32 irqenable_l[0x4]; 3157b646a6dSSimon Schwarz u32 sysstatus; 3167b646a6dSSimon Schwarz u32 ocp_sysconfig; 3177b646a6dSSimon Schwarz u8 res2[0x34]; 3187b646a6dSSimon Schwarz u32 caps_0; 3197b646a6dSSimon Schwarz u8 res3[0x4]; 3207b646a6dSSimon Schwarz u32 caps_2; 3217b646a6dSSimon Schwarz u32 caps_3; 3227b646a6dSSimon Schwarz u32 caps_4; 3237b646a6dSSimon Schwarz u32 gcr; 3247b646a6dSSimon Schwarz u8 res4[0x4]; 3257b646a6dSSimon Schwarz struct dma4_chan chan[32]; 3267b646a6dSSimon Schwarz }; 3277b646a6dSSimon Schwarz 3287b646a6dSSimon Schwarz #endif /*__ASSEMBLY__ */ 3297b646a6dSSimon Schwarz #endif /* __KERNEL_STRICT_NAMES */ 3307b646a6dSSimon Schwarz 331819833afSPeter Tyser /* timer regs offsets (32 bit regs) */ 332819833afSPeter Tyser 333819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 334819833afSPeter Tyser #ifndef __ASSEMBLY__ 335819833afSPeter Tyser struct gptimer { 336819833afSPeter Tyser u32 tidr; /* 0x00 r */ 337819833afSPeter Tyser u8 res[0xc]; 338819833afSPeter Tyser u32 tiocp_cfg; /* 0x10 rw */ 339819833afSPeter Tyser u32 tistat; /* 0x14 r */ 340819833afSPeter Tyser u32 tisr; /* 0x18 rw */ 341819833afSPeter Tyser u32 tier; /* 0x1c rw */ 342819833afSPeter Tyser u32 twer; /* 0x20 rw */ 343819833afSPeter Tyser u32 tclr; /* 0x24 rw */ 344819833afSPeter Tyser u32 tcrr; /* 0x28 rw */ 345819833afSPeter Tyser u32 tldr; /* 0x2c rw */ 346819833afSPeter Tyser u32 ttgr; /* 0x30 rw */ 347819833afSPeter Tyser u32 twpc; /* 0x34 r*/ 348819833afSPeter Tyser u32 tmar; /* 0x38 rw*/ 349819833afSPeter Tyser u32 tcar1; /* 0x3c r */ 350819833afSPeter Tyser u32 tcicr; /* 0x40 rw */ 351819833afSPeter Tyser u32 tcar2; /* 0x44 r */ 352819833afSPeter Tyser }; 353819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 354819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 355819833afSPeter Tyser 356819833afSPeter Tyser /* enable sys_clk NO-prescale /1 */ 357819833afSPeter Tyser #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 358819833afSPeter Tyser 359819833afSPeter Tyser /* Watchdog */ 360819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 361819833afSPeter Tyser #ifndef __ASSEMBLY__ 362819833afSPeter Tyser struct watchdog { 363819833afSPeter Tyser u8 res1[0x34]; 364819833afSPeter Tyser u32 wwps; /* 0x34 r */ 365819833afSPeter Tyser u8 res2[0x10]; 366819833afSPeter Tyser u32 wspr; /* 0x48 rw */ 367819833afSPeter Tyser }; 368819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 369819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 370819833afSPeter Tyser 371819833afSPeter Tyser #define WD_UNLOCK1 0xAAAA 372819833afSPeter Tyser #define WD_UNLOCK2 0x5555 373819833afSPeter Tyser 374819833afSPeter Tyser /* PRCM */ 375819833afSPeter Tyser #define PRCM_BASE 0x48004000 376819833afSPeter Tyser 377819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 378819833afSPeter Tyser #ifndef __ASSEMBLY__ 379819833afSPeter Tyser struct prcm { 380819833afSPeter Tyser u32 fclken_iva2; /* 0x00 */ 381819833afSPeter Tyser u32 clken_pll_iva2; /* 0x04 */ 382819833afSPeter Tyser u8 res1[0x1c]; 383819833afSPeter Tyser u32 idlest_pll_iva2; /* 0x24 */ 384819833afSPeter Tyser u8 res2[0x18]; 385819833afSPeter Tyser u32 clksel1_pll_iva2 ; /* 0x40 */ 386819833afSPeter Tyser u32 clksel2_pll_iva2; /* 0x44 */ 387819833afSPeter Tyser u8 res3[0x8bc]; 388819833afSPeter Tyser u32 clken_pll_mpu; /* 0x904 */ 389819833afSPeter Tyser u8 res4[0x1c]; 390819833afSPeter Tyser u32 idlest_pll_mpu; /* 0x924 */ 391819833afSPeter Tyser u8 res5[0x18]; 392819833afSPeter Tyser u32 clksel1_pll_mpu; /* 0x940 */ 393819833afSPeter Tyser u32 clksel2_pll_mpu; /* 0x944 */ 394819833afSPeter Tyser u8 res6[0xb8]; 395819833afSPeter Tyser u32 fclken1_core; /* 0xa00 */ 3967b89795fSAlexander Holler u32 res_fclken2_core; 3977b89795fSAlexander Holler u32 fclken3_core; /* 0xa08 */ 3987b89795fSAlexander Holler u8 res7[0x4]; 399819833afSPeter Tyser u32 iclken1_core; /* 0xa10 */ 400819833afSPeter Tyser u32 iclken2_core; /* 0xa14 */ 4017b89795fSAlexander Holler u32 iclken3_core; /* 0xa18 */ 4027b89795fSAlexander Holler u8 res8[0x24]; 403819833afSPeter Tyser u32 clksel_core; /* 0xa40 */ 404819833afSPeter Tyser u8 res9[0xbc]; 405819833afSPeter Tyser u32 fclken_gfx; /* 0xb00 */ 406819833afSPeter Tyser u8 res10[0xc]; 407819833afSPeter Tyser u32 iclken_gfx; /* 0xb10 */ 408819833afSPeter Tyser u8 res11[0x2c]; 409819833afSPeter Tyser u32 clksel_gfx; /* 0xb40 */ 410819833afSPeter Tyser u8 res12[0xbc]; 411819833afSPeter Tyser u32 fclken_wkup; /* 0xc00 */ 412819833afSPeter Tyser u8 res13[0xc]; 413819833afSPeter Tyser u32 iclken_wkup; /* 0xc10 */ 414819833afSPeter Tyser u8 res14[0xc]; 415819833afSPeter Tyser u32 idlest_wkup; /* 0xc20 */ 416819833afSPeter Tyser u8 res15[0x1c]; 417819833afSPeter Tyser u32 clksel_wkup; /* 0xc40 */ 418819833afSPeter Tyser u8 res16[0xbc]; 419819833afSPeter Tyser u32 clken_pll; /* 0xd00 */ 4207b89795fSAlexander Holler u32 clken2_pll; /* 0xd04 */ 4217b89795fSAlexander Holler u8 res17[0x18]; 422819833afSPeter Tyser u32 idlest_ckgen; /* 0xd20 */ 4237b89795fSAlexander Holler u32 idlest2_ckgen; /* 0xd24 */ 4247b89795fSAlexander Holler u8 res18[0x18]; 425819833afSPeter Tyser u32 clksel1_pll; /* 0xd40 */ 426819833afSPeter Tyser u32 clksel2_pll; /* 0xd44 */ 427819833afSPeter Tyser u32 clksel3_pll; /* 0xd48 */ 4287b89795fSAlexander Holler u32 clksel4_pll; /* 0xd4c */ 4297b89795fSAlexander Holler u32 clksel5_pll; /* 0xd50 */ 4307b89795fSAlexander Holler u8 res19[0xac]; 431819833afSPeter Tyser u32 fclken_dss; /* 0xe00 */ 432819833afSPeter Tyser u8 res20[0xc]; 433819833afSPeter Tyser u32 iclken_dss; /* 0xe10 */ 434819833afSPeter Tyser u8 res21[0x2c]; 435819833afSPeter Tyser u32 clksel_dss; /* 0xe40 */ 436819833afSPeter Tyser u8 res22[0xbc]; 437819833afSPeter Tyser u32 fclken_cam; /* 0xf00 */ 438819833afSPeter Tyser u8 res23[0xc]; 439819833afSPeter Tyser u32 iclken_cam; /* 0xf10 */ 440819833afSPeter Tyser u8 res24[0x2c]; 441819833afSPeter Tyser u32 clksel_cam; /* 0xf40 */ 442819833afSPeter Tyser u8 res25[0xbc]; 443819833afSPeter Tyser u32 fclken_per; /* 0x1000 */ 444819833afSPeter Tyser u8 res26[0xc]; 445819833afSPeter Tyser u32 iclken_per; /* 0x1010 */ 446819833afSPeter Tyser u8 res27[0x2c]; 447819833afSPeter Tyser u32 clksel_per; /* 0x1040 */ 448819833afSPeter Tyser u8 res28[0xfc]; 449819833afSPeter Tyser u32 clksel1_emu; /* 0x1140 */ 4507b89795fSAlexander Holler u8 res29[0x2bc]; 4517b89795fSAlexander Holler u32 fclken_usbhost; /* 0x1400 */ 4527b89795fSAlexander Holler u8 res30[0xc]; 4537b89795fSAlexander Holler u32 iclken_usbhost; /* 0x1410 */ 454819833afSPeter Tyser }; 455819833afSPeter Tyser #else /* __ASSEMBLY__ */ 456819833afSPeter Tyser #define CM_CLKSEL_CORE 0x48004a40 457819833afSPeter Tyser #define CM_CLKSEL_GFX 0x48004b40 458819833afSPeter Tyser #define CM_CLKSEL_WKUP 0x48004c40 459819833afSPeter Tyser #define CM_CLKEN_PLL 0x48004d00 460819833afSPeter Tyser #define CM_CLKSEL1_PLL 0x48004d40 461819833afSPeter Tyser #define CM_CLKSEL1_EMU 0x48005140 462819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 463819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 464819833afSPeter Tyser 465819833afSPeter Tyser #define PRM_BASE 0x48306000 466819833afSPeter Tyser 467819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 468819833afSPeter Tyser #ifndef __ASSEMBLY__ 469819833afSPeter Tyser struct prm { 470819833afSPeter Tyser u8 res1[0xd40]; 471819833afSPeter Tyser u32 clksel; /* 0xd40 */ 472819833afSPeter Tyser u8 res2[0x50c]; 473819833afSPeter Tyser u32 rstctrl; /* 0x1250 */ 474819833afSPeter Tyser u8 res3[0x1c]; 475819833afSPeter Tyser u32 clksrc_ctrl; /* 0x1270 */ 476819833afSPeter Tyser }; 477819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 478819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 479819833afSPeter Tyser 480d417d1dbSSRICHARAN R #define PRM_RSTCTRL 0x48307250 481d417d1dbSSRICHARAN R #define PRM_RSTCTRL_RESET 0x04 482*70239507SLokesh Vutla #define PRM_RSTST 0x48307258 483*70239507SLokesh Vutla #define PRM_RSTST_WARM_RESET_MASK 0x7D2 484819833afSPeter Tyser #define SYSCLKDIV_1 (0x1 << 6) 485819833afSPeter Tyser #define SYSCLKDIV_2 (0x1 << 7) 486819833afSPeter Tyser 487819833afSPeter Tyser #define CLKSEL_GPT1 (0x1 << 0) 488819833afSPeter Tyser 489819833afSPeter Tyser #define EN_GPT1 (0x1 << 0) 490819833afSPeter Tyser #define EN_32KSYNC (0x1 << 2) 491819833afSPeter Tyser 492819833afSPeter Tyser #define ST_WDT2 (0x1 << 5) 493819833afSPeter Tyser 494819833afSPeter Tyser #define ST_MPU_CLK (0x1 << 0) 495819833afSPeter Tyser 496819833afSPeter Tyser #define ST_CORE_CLK (0x1 << 0) 497819833afSPeter Tyser 498819833afSPeter Tyser #define ST_PERIPH_CLK (0x1 << 1) 499819833afSPeter Tyser 500819833afSPeter Tyser #define ST_IVA2_CLK (0x1 << 0) 501819833afSPeter Tyser 502819833afSPeter Tyser #define RESETDONE (0x1 << 0) 503819833afSPeter Tyser 504819833afSPeter Tyser #define TCLR_ST (0x1 << 0) 505819833afSPeter Tyser #define TCLR_AR (0x1 << 1) 506819833afSPeter Tyser #define TCLR_PRE (0x1 << 5) 507819833afSPeter Tyser 508819833afSPeter Tyser /* SMX-APE */ 509819833afSPeter Tyser #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 510819833afSPeter Tyser #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 511819833afSPeter Tyser #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 512819833afSPeter Tyser #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 513819833afSPeter Tyser 514819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 515819833afSPeter Tyser #ifndef __ASSEMBLY__ 516819833afSPeter Tyser struct pm { 517819833afSPeter Tyser u8 res1[0x48]; 518819833afSPeter Tyser u32 req_info_permission_0; /* 0x48 */ 519819833afSPeter Tyser u8 res2[0x4]; 520819833afSPeter Tyser u32 read_permission_0; /* 0x50 */ 521819833afSPeter Tyser u8 res3[0x4]; 522819833afSPeter Tyser u32 wirte_permission_0; /* 0x58 */ 523819833afSPeter Tyser u8 res4[0x4]; 524819833afSPeter Tyser u32 addr_match_1; /* 0x58 */ 525819833afSPeter Tyser u8 res5[0x4]; 526819833afSPeter Tyser u32 req_info_permission_1; /* 0x68 */ 527819833afSPeter Tyser u8 res6[0x14]; 528819833afSPeter Tyser u32 addr_match_2; /* 0x80 */ 529819833afSPeter Tyser }; 530819833afSPeter Tyser #endif /*__ASSEMBLY__ */ 531819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 532819833afSPeter Tyser 533819833afSPeter Tyser /* Permission values for registers -Full fledged permissions to all */ 534819833afSPeter Tyser #define UNLOCK_1 0xFFFFFFFF 535819833afSPeter Tyser #define UNLOCK_2 0x00000000 536819833afSPeter Tyser #define UNLOCK_3 0x0000FFFF 537819833afSPeter Tyser 538819833afSPeter Tyser #define NOT_EARLY 0 539819833afSPeter Tyser 540819833afSPeter Tyser /* I2C base */ 541819833afSPeter Tyser #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) 542819833afSPeter Tyser #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) 543819833afSPeter Tyser #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) 544819833afSPeter Tyser 5459b167577SSteve Sakoman /* MUSB base */ 5469b167577SSteve Sakoman #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) 5479b167577SSteve Sakoman 54825223a68SAneesh V /* OMAP3 GPIO registers */ 54925223a68SAneesh V #define OMAP_GPIO_REVISION 0x0000 55025223a68SAneesh V #define OMAP_GPIO_SYSCONFIG 0x0010 55125223a68SAneesh V #define OMAP_GPIO_SYSSTATUS 0x0014 55225223a68SAneesh V #define OMAP_GPIO_IRQSTATUS1 0x0018 55325223a68SAneesh V #define OMAP_GPIO_IRQSTATUS2 0x0028 55425223a68SAneesh V #define OMAP_GPIO_IRQENABLE2 0x002c 55525223a68SAneesh V #define OMAP_GPIO_IRQENABLE1 0x001c 55625223a68SAneesh V #define OMAP_GPIO_WAKE_EN 0x0020 55725223a68SAneesh V #define OMAP_GPIO_CTRL 0x0030 55825223a68SAneesh V #define OMAP_GPIO_OE 0x0034 55925223a68SAneesh V #define OMAP_GPIO_DATAIN 0x0038 56025223a68SAneesh V #define OMAP_GPIO_DATAOUT 0x003c 56125223a68SAneesh V #define OMAP_GPIO_LEVELDETECT0 0x0040 56225223a68SAneesh V #define OMAP_GPIO_LEVELDETECT1 0x0044 56325223a68SAneesh V #define OMAP_GPIO_RISINGDETECT 0x0048 56425223a68SAneesh V #define OMAP_GPIO_FALLINGDETECT 0x004c 56525223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_EN 0x0050 56625223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_VAL 0x0054 56725223a68SAneesh V #define OMAP_GPIO_CLEARIRQENABLE1 0x0060 56825223a68SAneesh V #define OMAP_GPIO_SETIRQENABLE1 0x0064 56925223a68SAneesh V #define OMAP_GPIO_CLEARWKUENA 0x0080 57025223a68SAneesh V #define OMAP_GPIO_SETWKUENA 0x0084 57125223a68SAneesh V #define OMAP_GPIO_CLEARDATAOUT 0x0090 57225223a68SAneesh V #define OMAP_GPIO_SETDATAOUT 0x0094 57325223a68SAneesh V 574819833afSPeter Tyser #endif /* _CPU_H */ 575